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/kernel/linux/linux-5.10/drivers/dma/
Dimg-mdc-dma.c118 struct mdc_dma *mdma; member
149 static inline u32 mdc_readl(struct mdc_dma *mdma, u32 reg) in mdc_readl() argument
151 return readl(mdma->regs + reg); in mdc_readl()
154 static inline void mdc_writel(struct mdc_dma *mdma, u32 val, u32 reg) in mdc_writel() argument
156 writel(val, mdma->regs + reg); in mdc_writel()
161 return mdc_readl(mchan->mdma, mchan->chan_nr * 0x040 + reg); in mdc_chan_readl()
166 mdc_writel(mchan->mdma, val, mchan->chan_nr * 0x040 + reg); in mdc_chan_writel()
181 static inline struct device *mdma2dev(struct mdc_dma *mdma) in mdma2dev() argument
183 return mdma->dma_dev.dev; in mdma2dev()
210 struct mdc_dma *mdma = mchan->mdma; in mdc_list_desc_config() local
[all …]
Dmpc512x_dma.c256 struct mpc_dma *mdma = dma_chan_to_mpc_dma(&mchan->chan); in mpc_dma_execute() local
300 memcpy_toio(&mdma->tcd[cid], first->tcd, sizeof(struct mpc_dma_tcd)); in mpc_dma_execute()
303 mdma->tcd[cid].e_sg = 1; in mpc_dma_execute()
305 if (mdma->is_mpc8308) { in mpc_dma_execute()
307 out_8(&mdma->regs->dmassrt, cid); in mpc_dma_execute()
310 out_8(&mdma->regs->dmaserq, cid); in mpc_dma_execute()
313 out_8(&mdma->regs->dmassrt, cid); in mpc_dma_execute()
318 static void mpc_dma_irq_process(struct mpc_dma *mdma, u32 is, u32 es, int off) in mpc_dma_irq_process() argument
327 mchan = &mdma->channels[ch + off]; in mpc_dma_irq_process()
331 out_8(&mdma->regs->dmacint, ch + off); in mpc_dma_irq_process()
[all …]
Dstm32-mdma.c8 * Driver for STM32 MDMA controller
35 /* MDMA Generic getter/setter */
42 #define STM32_MDMA_GISR0 0x0000 /* MDMA Int Status Reg 1 */
44 /* MDMA Channel x interrupt/status register */
53 /* MDMA Channel x interrupt flag clear register */
66 /* MDMA Channel x error status register */
75 /* MDMA Channel x control register */
96 /* MDMA Channel x transfer configuration register */
150 /* MDMA Channel x block number of data register */
164 /* MDMA Channel x source address register */
[all …]
/kernel/linux/linux-6.6/drivers/dma/
Dimg-mdc-dma.c117 struct mdc_dma *mdma; member
148 static inline u32 mdc_readl(struct mdc_dma *mdma, u32 reg) in mdc_readl() argument
150 return readl(mdma->regs + reg); in mdc_readl()
153 static inline void mdc_writel(struct mdc_dma *mdma, u32 val, u32 reg) in mdc_writel() argument
155 writel(val, mdma->regs + reg); in mdc_writel()
160 return mdc_readl(mchan->mdma, mchan->chan_nr * 0x040 + reg); in mdc_chan_readl()
165 mdc_writel(mchan->mdma, val, mchan->chan_nr * 0x040 + reg); in mdc_chan_writel()
180 static inline struct device *mdma2dev(struct mdc_dma *mdma) in mdma2dev() argument
182 return mdma->dma_dev.dev; in mdma2dev()
209 struct mdc_dma *mdma = mchan->mdma; in mdc_list_desc_config() local
[all …]
Dmpc512x_dma.c256 struct mpc_dma *mdma = dma_chan_to_mpc_dma(&mchan->chan); in mpc_dma_execute() local
300 memcpy_toio(&mdma->tcd[cid], first->tcd, sizeof(struct mpc_dma_tcd)); in mpc_dma_execute()
303 mdma->tcd[cid].e_sg = 1; in mpc_dma_execute()
305 if (mdma->is_mpc8308) { in mpc_dma_execute()
307 out_8(&mdma->regs->dmassrt, cid); in mpc_dma_execute()
310 out_8(&mdma->regs->dmaserq, cid); in mpc_dma_execute()
313 out_8(&mdma->regs->dmassrt, cid); in mpc_dma_execute()
318 static void mpc_dma_irq_process(struct mpc_dma *mdma, u32 is, u32 es, int off) in mpc_dma_irq_process() argument
327 mchan = &mdma->channels[ch + off]; in mpc_dma_irq_process()
331 out_8(&mdma->regs->dmacint, ch + off); in mpc_dma_irq_process()
[all …]
Dstm32-mdma.c8 * Driver for STM32 MDMA controller
35 #define STM32_MDMA_GISR0 0x0000 /* MDMA Int Status Reg 1 */
37 /* MDMA Channel x interrupt/status register */
46 /* MDMA Channel x interrupt flag clear register */
59 /* MDMA Channel x error status register */
68 /* MDMA Channel x control register */
89 /* MDMA Channel x transfer configuration register */
128 /* MDMA Channel x block number of data register */
139 /* MDMA Channel x source address register */
142 /* MDMA Channel x destination address register */
[all …]
Dstm32-dma.c198 * struct stm32_dma_mdma_config - STM32 DMA MDMA configuration
199 * @stream_id: DMA request to trigger STM32 MDMA transfer
201 * used by STM32 MDMA to clear DMA Transfer Complete flag
405 /* Check if user is requesting DMA to trigger STM32 MDMA */ in stm32_dma_slave_config()
587 /* When DMA triggers STM32 MDMA, DMA Transfer Complete is managed by STM32 MDMA */ in stm32_dma_start_transfer()
1115 /* Activate Double Buffer Mode if DMA triggers STM32 MDMA and more than 1 sg */ in stm32_dma_prep_slave_sg()
/kernel/linux/linux-6.6/Documentation/arch/arm/stm32/
Dstm32-dma-mdma-chaining.rst4 STM32 DMA-MDMA chaining
11 This document describes the STM32 DMA-MDMA chaining feature. But before going
17 STM32MP1 SoCs embed both STM32 DMA and STM32 MDMA controllers. STM32 DMA
33 **STM32 MDMA**
35 STM32 MDMA (Master DMA) is mainly used to manage direct data transfers between
38 interfaces for AHB peripherals, while the STM32 MDMA acts as a second level
39 DMA with better performance. As a AXI/AHB master, STM32 MDMA can take control
46 STM32 DMA-MDMA chaining feature relies on the strengths of STM32 DMA and
47 STM32 MDMA controllers.
52 counter is automatically reloaded. This allows the SW or the STM32 MDMA to
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/dma/
Dst,stm32-mdma.yaml4 $id: http://devicetree.org/schemas/dma/st,stm32-mdma.yaml#
7 title: STMicroelectronics STM32 MDMA Controller
10 The STM32 MDMA is a general-purpose direct memory access controller capable of
12 DMA clients connected to the STM32 MDMA controller must use the format
14 a phandle to the MDMA controller plus the following five integer cells:
43 0x00: Each MDMA request triggers a buffer transfer (max 128 bytes)
44 0x1: Each MDMA request triggers a block transfer (max 64K bytes)
45 0x2: Each MDMA request triggers a repeated block transfer
46 0x3: Each MDMA request triggers a linked list transfer
48 if no HW ack signal is used by the MDMA client
[all …]
Dingenic,dma.yaml24 - ingenic,jz4760-mdma
27 - ingenic,jz4760b-mdma
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/dma/
Dst,stm32-mdma.yaml4 $id: http://devicetree.org/schemas/dma/st,stm32-mdma.yaml#
7 title: STMicroelectronics STM32 MDMA Controller bindings
10 The STM32 MDMA is a general-purpose direct memory access controller capable of
12 DMA clients connected to the STM32 MDMA controller must use the format
14 a phandle to the MDMA controller plus the following five integer cells:
43 0x00: Each MDMA request triggers a buffer transfer (max 128 bytes)
44 0x1: Each MDMA request triggers a block transfer (max 64K bytes)
45 0x2: Each MDMA request triggers a repeated block transfer
46 0x3: Each MDMA request triggers a linked list transfer
48 if no HW ack signal is used by the MDMA client
[all …]
/kernel/linux/linux-5.10/drivers/ata/
Dpata_pdc2027x.c92 { 0xdf, 0x5f }, /* MDMA mode 0 */
93 { 0x6b, 0x27 }, /* MDMA mode 1 */
94 { 0x69, 0x25 }, /* MDMA mode 2 */
368 /* Set the MDMA timing registers with value table for 133MHz */ in pdc2027x_set_dmamode()
371 PDPRINTK("Set mdma regs... \n"); in pdc2027x_set_dmamode()
379 PDPRINTK("Set mdma regs done\n"); in pdc2027x_set_dmamode()
381 PDPRINTK("Set to mdma mode[%u] \n", mdma_mode); in pdc2027x_set_dmamode()
/kernel/linux/linux-5.10/drivers/dma/qcom/
Dhidma.c117 struct hidma_dev *mdma = to_hidma_dev(ddev); in hidma_process_completed() local
141 llstat = hidma_ll_status(mdma->lldev, mdesc->tre_ch); in hidma_process_completed()
405 struct hidma_dev *mdma = mchan->dmadev; in hidma_prep_dma_memcpy() local
420 hidma_ll_set_transfer_params(mdma->lldev, mdesc->tre_ch, in hidma_prep_dma_memcpy()
438 struct hidma_dev *mdma = mchan->dmadev; in hidma_prep_dma_memset() local
453 hidma_ll_set_transfer_params(mdma->lldev, mdesc->tre_ch, in hidma_prep_dma_memset()
533 struct hidma_dev *mdma = mchan->dmadev; in hidma_free_chan_resources() local
548 hidma_ll_free(mdma->lldev, mdesc->tre_ch); in hidma_free_chan_resources()
/kernel/linux/linux-6.6/drivers/dma/qcom/
Dhidma.c111 struct hidma_dev *mdma = to_hidma_dev(ddev); in hidma_process_completed() local
135 llstat = hidma_ll_status(mdma->lldev, mdesc->tre_ch); in hidma_process_completed()
398 struct hidma_dev *mdma = mchan->dmadev; in hidma_prep_dma_memcpy() local
413 hidma_ll_set_transfer_params(mdma->lldev, mdesc->tre_ch, in hidma_prep_dma_memcpy()
431 struct hidma_dev *mdma = mchan->dmadev; in hidma_prep_dma_memset() local
457 hidma_ll_set_transfer_params(mdma->lldev, mdesc->tre_ch, in hidma_prep_dma_memset()
537 struct hidma_dev *mdma = mchan->dmadev; in hidma_free_chan_resources() local
552 hidma_ll_free(mdma->lldev, mdesc->tre_ch); in hidma_free_chan_resources()
/kernel/linux/linux-5.10/drivers/rapidio/devices/
Dtsi721.c113 void __iomem *regs = priv->regs + TSI721_DMAC_BASE(priv->mdma.ch_id); in tsi721_maint_dma()
125 bd_ptr = priv->mdma.bd_base; in tsi721_maint_dma()
153 priv->mdma.ch_id, ch_stat); in tsi721_maint_dma()
1433 priv->mdma.ch_id = TSI721_DMACH_MAINT; in tsi721_bdma_maint_init()
1443 priv->mdma.bd_num = bd_num; in tsi721_bdma_maint_init()
1444 priv->mdma.bd_phys = bd_phys; in tsi721_bdma_maint_init()
1445 priv->mdma.bd_base = bd_ptr; in tsi721_bdma_maint_init()
1462 priv->mdma.bd_base = NULL; in tsi721_bdma_maint_init()
1466 priv->mdma.sts_phys = sts_phys; in tsi721_bdma_maint_init()
1467 priv->mdma.sts_base = sts_ptr; in tsi721_bdma_maint_init()
[all …]
/kernel/linux/linux-6.6/drivers/rapidio/devices/
Dtsi721.c113 void __iomem *regs = priv->regs + TSI721_DMAC_BASE(priv->mdma.ch_id); in tsi721_maint_dma()
125 bd_ptr = priv->mdma.bd_base; in tsi721_maint_dma()
153 priv->mdma.ch_id, ch_stat); in tsi721_maint_dma()
1433 priv->mdma.ch_id = TSI721_DMACH_MAINT; in tsi721_bdma_maint_init()
1443 priv->mdma.bd_num = bd_num; in tsi721_bdma_maint_init()
1444 priv->mdma.bd_phys = bd_phys; in tsi721_bdma_maint_init()
1445 priv->mdma.bd_base = bd_ptr; in tsi721_bdma_maint_init()
1462 priv->mdma.bd_base = NULL; in tsi721_bdma_maint_init()
1466 priv->mdma.sts_phys = sts_phys; in tsi721_bdma_maint_init()
1467 priv->mdma.sts_base = sts_ptr; in tsi721_bdma_maint_init()
[all …]
/kernel/linux/linux-6.6/drivers/ata/
Dpata_pdc2027x.c85 { 0xdf, 0x5f }, /* MDMA mode 0 */
86 { 0x6b, 0x27 }, /* MDMA mode 1 */
87 { 0x69, 0x25 }, /* MDMA mode 2 */
357 /* Set the MDMA timing registers with value table for 133MHz */ in pdc2027x_set_dmamode()
360 ata_port_dbg(ap, "Set mdma regs... \n"); in pdc2027x_set_dmamode()
369 ata_port_dbg(ap, "Set to mdma mode[%u] \n", mdma_mode); in pdc2027x_set_dmamode()
/kernel/linux/linux-6.6/Documentation/arch/arm/
Dindex.rst63 stm32/stm32-dma-mdma-chaining
/kernel/linux/linux-6.6/arch/arm/boot/dts/st/
Dstm32mp131.dtsi1213 mdma: dma-controller@58000000 { label
1214 compatible = "st,stm32h7-mdma";
1217 clocks = <&rcc MDMA>;
1248 dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>,
1249 <&mdma 24 0x2 0x12000a08 0x0 0x0>,
1250 <&mdma 25 0x2 0x12000a0a 0x0 0x0>;
1263 dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>,
1264 <&mdma 26 0x2 0x10100008 0x0 0x0>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/iommu/
Dti,omap-iommu.txt28 instance number should be 0 for DSP MDMA MMUs and 1 for
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/iommu/
Dti,omap-iommu.txt28 instance number should be 0 for DSP MDMA MMUs and 1 for
/kernel/linux/linux-5.10/drivers/ide/
Dpmac.c85 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
132 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
134 * of this one enables UDMA vs. MDMA, and bits 4..7 are the
180 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
636 * Calculate MDMA timings for all cells
694 printk(KERN_ERR "%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n", in set_timings_mdma()
722 /* Clear out mdma bits and disable udma */ in set_timings_mdma()
768 printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n", in set_timings_mdma()
/kernel/linux/linux-6.6/include/dt-bindings/clock/
Dstm32mp13-clks.h97 #define MDMA 69 macro
/kernel/linux/linux-6.6/arch/arm64/boot/dts/xilinx/
Dzynqmp-zc1751-xm017-dc3.dts128 arasan,has-mdma;
/kernel/linux/linux-5.10/include/dt-bindings/clock/
Dstm32mp1-clks.h113 #define MDMA 100 macro

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