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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/msm/
Dqcom,mdp5.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,mdp5.yaml#
7 title: Qualcomm Adreno/Snapdragon Mobile Display controller (MDP5)
10 MDP5 display controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994
20 - const: qcom,mdp5
24 - qcom,apq8084-mdp5
25 - qcom,msm8226-mdp5
26 - qcom,msm8916-mdp5
27 - qcom,msm8917-mdp5
28 - qcom,msm8953-mdp5
29 - qcom,msm8974-mdp5
[all …]
Dqcom,mdss.yaml15 encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc.
108 const: qcom,mdp5
182 compatible = "qcom,msm8916-mdp5", "qcom,mdp5";
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/
DMakefile43 disp/mdp5/mdp5_cfg.o \
44 disp/mdp5/mdp5_ctl.o \
45 disp/mdp5/mdp5_crtc.o \
46 disp/mdp5/mdp5_encoder.o \
47 disp/mdp5/mdp5_irq.o \
48 disp/mdp5/mdp5_mdss.o \
49 disp/mdp5/mdp5_kms.o \
50 disp/mdp5/mdp5_pipe.o \
51 disp/mdp5/mdp5_mixer.o \
52 disp/mdp5/mdp5_plane.o \
[all …]
DNOTES7 + MDP5 - snapdragon 800
49 For MDP5, the mapping is:
60 Also unlike MDP4, with MDP5 all the IRQs for other blocks (HDMI, DSI,
63 And finally, MDP5 has this "Shared Memory Pool" (called "SMP"), from
Dmsm_drv.h147 /* top level MDSS wrapper device (for MDP5/DPU only) */
151 * shared by both mdp4 and mdp5..
155 /* eDP is for mdp5 only, but kms has not been created
161 /* DSI is shared by mdp4 and mdp5 */
Dmsm_drv.c1144 * on MDP5 based platforms, the MDSS platform device is the component in add_components_mdp()
1145 * master that adds MDP5 and other display interface components to in add_components_mdp()
1204 * MDP5/DPU based devices don't have a flat hierarchy. There is a top in add_display_components()
1205 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc. in add_display_components()
1206 * Populate the children devices, find the MDP5/DPU node, and then add in add_display_components()
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/
DMakefile45 disp/mdp5/mdp5_cfg.o \
46 disp/mdp5/mdp5_cmd_encoder.o \
47 disp/mdp5/mdp5_ctl.o \
48 disp/mdp5/mdp5_crtc.o \
49 disp/mdp5/mdp5_encoder.o \
50 disp/mdp5/mdp5_irq.o \
51 disp/mdp5/mdp5_kms.o \
52 disp/mdp5/mdp5_pipe.o \
53 disp/mdp5/mdp5_mixer.o \
54 disp/mdp5/mdp5_plane.o \
[all …]
DNOTES7 + MDP5 - snapdragon 800
49 For MDP5, the mapping is:
60 Also unlike MDP4, with MDP5 all the IRQs for other blocks (HDMI, DSI,
63 And finally, MDP5 has this "Shared Memory Pool" (called "SMP"), from
DKconfig70 bool "Enable MDP5 support in MSM DRM driver"
75 Compile in support for the Mobile Display Processor v5 (MDP5) in
Dmsm_mdss.c262 * mdss on mdp5 hardware. Skip it for now. in msm_mdss_enable()
353 * MDP5 MDSS uses at most three specified clocks.
491 * MDP5/DPU based devices don't have a flat hierarchy. There is a top in mdss_probe()
492 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc. in mdss_probe()
493 * Populate the children devices, find the MDP5/DPU node, and then add in mdss_probe()
Dmsm_io_utils.c144 * If the MDP5/DPU device node doesn't have interconnects, lookup the in msm_icc_get()
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/msm/
Dmdp5.txt1 Qualcomm adreno/snapdragon MDP5 display controller
6 encapsulates sub-blocks like MDP5, DSI, HDMI, eDP etc, and the MDP5 display
36 MDP5:
39 * "qcom,mdp5" - MDP5
43 - interrupts: Interrupt line from MDP5 to MDSS interrupt controller.
112 compatible = "qcom,mdp5";
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_kms.c33 * W MDP5:0x2e0 0xe9 (mdss_mdp.c:839) in mdp5_hw_init()
34 * W MDP5:0x2e4 0x55 (mdss_mdp.c:839) in mdp5_hw_init()
35 * W MDP5:0x3ac 0xc0000ccc (mdss_mdp.c:839) in mdp5_hw_init()
36 * W MDP5:0x3b4 0xc0000ccc (mdss_mdp.c:839) in mdp5_hw_init()
37 * W MDP5:0x3bc 0xcccccc (mdss_mdp.c:839) in mdp5_hw_init()
38 * W MDP5:0x4a8 0xcccc0c0 (mdss_mdp.c:839) in mdp5_hw_init()
39 * W MDP5:0x4b0 0xccccc0c0 (mdss_mdp.c:839) in mdp5_hw_init()
40 * W MDP5:0x4b8 0xccccc000 (mdss_mdp.c:839) in mdp5_hw_init()
481 * the MDP5 interfaces) than the number of layer mixers present in HW, in modeset_init()
558 DRM_DEV_INFO(dev, "MDP5 version v%d.%d", *major, *minor); in read_mdp_hw_revision()
[all …]
Dmdp5_pipe.h10 /* TODO: Add SSPP_MAX in mdp5.xml.h */
Dmdp5_kms.h13 #include "mdp5_cfg.h" /* must be included before mdp5.xml.h */
14 #include "mdp5.xml.h"
Dmdp5_cfg.h14 * This module configures the dynamic offsets used by mdp5.xml.h
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_kms.c33 * W MDP5:0x2e0 0xe9 (mdss_mdp.c:839) in mdp5_hw_init()
34 * W MDP5:0x2e4 0x55 (mdss_mdp.c:839) in mdp5_hw_init()
35 * W MDP5:0x3ac 0xc0000ccc (mdss_mdp.c:839) in mdp5_hw_init()
36 * W MDP5:0x3b4 0xc0000ccc (mdss_mdp.c:839) in mdp5_hw_init()
37 * W MDP5:0x3bc 0xcccccc (mdss_mdp.c:839) in mdp5_hw_init()
38 * W MDP5:0x4a8 0xcccc0c0 (mdss_mdp.c:839) in mdp5_hw_init()
39 * W MDP5:0x4b0 0xccccc0c0 (mdss_mdp.c:839) in mdp5_hw_init()
40 * W MDP5:0x4b8 0xccccc000 (mdss_mdp.c:839) in mdp5_hw_init()
456 * the MDP5 interfaces) than the number of layer mixers present in HW, in modeset_init()
529 DRM_DEV_INFO(dev, "MDP5 version v%d.%d", *major, *minor); in read_mdp_hw_revision()
[all …]
Dmdp5_pipe.h10 /* TODO: Add SSPP_MAX in mdp5.xml.h */
Dmdp5_kms.h13 #include "mdp5_cfg.h" /* must be included before mdp5.xml.h */
14 #include "mdp5.xml.h"
Dmdp5_cfg.h14 * This module configures the dynamic offsets used by mdp5.xml.h
/kernel/linux/linux-6.6/arch/arm64/boot/dts/qcom/
Dsdm660.dtsi145 compatible = "qcom,sdm660-mdp5", "qcom,mdp5";
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/hdmi/
Dqfprom.xml.h15 - /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:…
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/
Dmdp_kms.c35 /* if an mdp_irq's irqmask has changed, such as when mdp5 crtc<->encoder
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/
Dmdp_kms.c35 /* if an mdp_irq's irqmask has changed, such as when mdp5 crtc<->encoder
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/dsi/
Dsfpb.xml.h15 - /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:…

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