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/kernel/linux/linux-6.6/drivers/input/serio/
Dhil_mlc.c2 * HIL MLC state machine and serio interface driver
37 * few bits of logic in addition to raw access to the HIL MLC,
44 * each time it runs, checking each MLC's progress at the current
45 * node in the state machine, and moving the MLC to subsequent nodes
66 MODULE_DESCRIPTION("HIL MLC serio");
72 #define PREFIX "HIL MLC: "
87 static void hil_mlc_clear_di_map(hil_mlc *mlc, int val) in hil_mlc_clear_di_map() argument
92 mlc->di_map[j] = -1; in hil_mlc_clear_di_map()
95 static void hil_mlc_clear_di_scratch(hil_mlc *mlc) in hil_mlc_clear_di_scratch() argument
97 memset(&mlc->di_scratch, 0, sizeof(mlc->di_scratch)); in hil_mlc_clear_di_scratch()
[all …]
Dhp_sdc_mlc.c2 * Access to HP-HIL MLC through HP System Device Controller.
45 #define PREFIX "HP SDC MLC: "
50 MODULE_DESCRIPTION("Glue for onboard HIL MLC in HP-PARISC machines");
65 hil_mlc *mlc = &hp_sdc_mlc; in hp_sdc_mlc_isr() local
67 write_lock(&mlc->lock); in hp_sdc_mlc_isr()
68 if (mlc->icount < 0) { in hp_sdc_mlc_isr()
70 up(&mlc->isem); in hp_sdc_mlc_isr()
73 idx = 15 - mlc->icount; in hp_sdc_mlc_isr()
75 mlc->ipacket[idx] |= data | HIL_ERR_INT; in hp_sdc_mlc_isr()
76 mlc->icount--; in hp_sdc_mlc_isr()
[all …]
/kernel/linux/linux-5.10/drivers/input/serio/
Dhil_mlc.c2 * HIL MLC state machine and serio interface driver
37 * few bits of logic in addition to raw access to the HIL MLC,
44 * each time it runs, checking each MLC's progress at the current
45 * node in the state machine, and moving the MLC to subsequent nodes
66 MODULE_DESCRIPTION("HIL MLC serio");
72 #define PREFIX "HIL MLC: "
87 static void hil_mlc_clear_di_map(hil_mlc *mlc, int val) in hil_mlc_clear_di_map() argument
92 mlc->di_map[j] = -1; in hil_mlc_clear_di_map()
95 static void hil_mlc_clear_di_scratch(hil_mlc *mlc) in hil_mlc_clear_di_scratch() argument
97 memset(&mlc->di_scratch, 0, sizeof(mlc->di_scratch)); in hil_mlc_clear_di_scratch()
[all …]
Dhp_sdc_mlc.c2 * Access to HP-HIL MLC through HP System Device Controller.
45 #define PREFIX "HP SDC MLC: "
50 MODULE_DESCRIPTION("Glue for onboard HIL MLC in HP-PARISC machines");
65 hil_mlc *mlc = &hp_sdc_mlc; in hp_sdc_mlc_isr() local
67 write_lock(&mlc->lock); in hp_sdc_mlc_isr()
68 if (mlc->icount < 0) { in hp_sdc_mlc_isr()
70 up(&mlc->isem); in hp_sdc_mlc_isr()
73 idx = 15 - mlc->icount; in hp_sdc_mlc_isr()
75 mlc->ipacket[idx] |= data | HIL_ERR_INT; in hp_sdc_mlc_isr()
76 mlc->icount--; in hp_sdc_mlc_isr()
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mtd/
Dlpc32xx-mlc.txt1 NXP LPC32xx SoC NAND MLC controller
4 - compatible: "nxp,lpc3220-mlc"
10 User Manual 7.5.14 MLC NAND Timing Register (the values here are specified in
26 mlc: flash@200a8000 {
27 compatible = "nxp,lpc3220-mlc";
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/
Dlpc32xx-mlc.txt1 NXP LPC32xx SoC NAND MLC controller
4 - compatible: "nxp,lpc3220-mlc"
10 User Manual 7.5.14 MLC NAND Timing Register (the values here are specified in
26 mlc: flash@200a8000 {
27 compatible = "nxp,lpc3220-mlc";
/kernel/linux/linux-6.6/include/linux/
Dhil_mlc.h91 typedef int (hilse_func) (hil_mlc *mlc, int arg);
105 typedef int (hil_mlc_cts) (hil_mlc *mlc);
106 typedef int (hil_mlc_out) (hil_mlc *mlc);
107 typedef int (hil_mlc_in) (hil_mlc *mlc, suseconds_t timeout);
117 hil_mlc *mlc; member
130 void *priv; /* Data specific to a particular type of MLC */
167 int hil_mlc_register(hil_mlc *mlc);
168 int hil_mlc_unregister(hil_mlc *mlc);
Dhp_sdc.h102 #define HP_SDC_STATUS_HILCMD 0x50 /* Command from HIL MLC */
103 #define HP_SDC_STATUS_HILDATA 0x60 /* Data from HIL MLC */
144 #define HP_SDC_IM_HIL 0x01 /* Mask the HIL MLC irq */
148 #define HP_SDC_CFG_NEW 0x20 /* Supports/uses HIL MLC */
158 #define HP_SDC_LPC_APE_IPF 0x01 /* HIL MLC APE/IPF (autopoll) set */
246 HIL MLC R0,R1 i8042 HIL watchdog */
248 /* Values used to (de)mangle input/output to/from the HIL MLC */
250 #define HP_SDC_HIL_CMD 0x50 /* Data from HIL MLC R1/8042 */
251 #define HP_SDC_HIL_R1MASK 0x0f /* Contents of HIL MLC R1 0:3 */
255 #define HP_SDC_HIL_ERR 0x81 /* HIL MLC R2 had a bit set */
[all …]
Dhil.h57 * implementing a software MLC to run HIL devices on a non-parisc machine.
101 /* The HIL MLC also has several error/status/control bits. We extend the
102 * "packet" to include these when direct access to the MLC is available,
105 * This way the device driver knows that the underlying MLC driver
109 HIL_ERR_OB = 0x00000800, /* MLC is busy sending an auto-poll,
/kernel/linux/linux-5.10/include/linux/
Dhil_mlc.h91 typedef int (hilse_func) (hil_mlc *mlc, int arg);
105 typedef int (hil_mlc_cts) (hil_mlc *mlc);
106 typedef int (hil_mlc_out) (hil_mlc *mlc);
107 typedef int (hil_mlc_in) (hil_mlc *mlc, suseconds_t timeout);
117 hil_mlc *mlc; member
130 void *priv; /* Data specific to a particular type of MLC */
167 int hil_mlc_register(hil_mlc *mlc);
168 int hil_mlc_unregister(hil_mlc *mlc);
Dhp_sdc.h102 #define HP_SDC_STATUS_HILCMD 0x50 /* Command from HIL MLC */
103 #define HP_SDC_STATUS_HILDATA 0x60 /* Data from HIL MLC */
144 #define HP_SDC_IM_HIL 0x01 /* Mask the HIL MLC irq */
148 #define HP_SDC_CFG_NEW 0x20 /* Supports/uses HIL MLC */
158 #define HP_SDC_LPC_APE_IPF 0x01 /* HIL MLC APE/IPF (autopoll) set */
246 HIL MLC R0,R1 i8042 HIL watchdog */
248 /* Values used to (de)mangle input/output to/from the HIL MLC */
250 #define HP_SDC_HIL_CMD 0x50 /* Data from HIL MLC R1/8042 */
251 #define HP_SDC_HIL_R1MASK 0x0f /* Contents of HIL MLC R1 0:3 */
255 #define HP_SDC_HIL_ERR 0x81 /* HIL MLC R2 had a bit set */
[all …]
Dhil.h57 * implementing a software MLC to run HIL devices on a non-parisc machine.
101 /* The HIL MLC also has several error/status/control bits. We extend the
102 * "packet" to include these when direct access to the MLC is available,
105 * This way the device driver knows that the underlying MLC driver
109 HIL_ERR_OB = 0x00000800, /* MLC is busy sending an auto-poll,
/kernel/linux/linux-6.6/arch/arm/mach-lpc32xx/
Dphy3250.c27 .bus_id = "nand-mlc",
28 .min_signal = 12, /* MLC NAND Flash */
67 OF_DEV_AUXDATA("nxp,lpc3220-mlc", 0x200a8000, "200a8000.flash",
/kernel/linux/linux-5.10/arch/arm/mach-lpc32xx/
Dphy3250.c27 .bus_id = "nand-mlc",
28 .min_signal = 12, /* MLC NAND Flash */
67 OF_DEV_AUXDATA("nxp,lpc3220-mlc", 0x200a8000, "200a8000.flash",
/kernel/linux/linux-5.10/drivers/mtd/nand/raw/
Dlpc32xx_mlc.c3 * Driver for NAND MLC Controller in LPC32xx
39 * MLC NAND controller register offsets
236 /* Reset MLC controller */ in lpc32xx_nand_setup()
240 /* Get base clock for MLC block */ in lpc32xx_nand_setup()
249 /* Configure MLC Controller: Large Block, 5 Byte Address */ in lpc32xx_nand_setup()
540 /* Auto Encode w/ Bit 8 = 0 (see LPC MLC Controller manual) */ in lpc32xx_write_page_lowlevel()
554 /* Read whole page - necessary with MLC controller! */ in lpc32xx_read_oob()
562 /* None, write_oob conflicts with the automatic LPC MLC ECC decoder! */ in lpc32xx_write_oob()
566 /* Prepares MLC for transfers with H/W ECC enabled: always enabled anyway */
585 "nand-mlc"); in lpc32xx_dma_setup()
[all …]
DKconfig205 tristate "NXP LPC32xx MLC NAND controller"
209 Uses the LPC32XX MLC (i.e. for Multi Level Cell chips) NAND
214 by the MLC NAND controller.
/kernel/linux/linux-6.6/drivers/mtd/nand/raw/
Dlpc32xx_mlc.c3 * Driver for NAND MLC Controller in LPC32xx
38 * MLC NAND controller register offsets
235 /* Reset MLC controller */ in lpc32xx_nand_setup()
239 /* Get base clock for MLC block */ in lpc32xx_nand_setup()
248 /* Configure MLC Controller: Large Block, 5 Byte Address */ in lpc32xx_nand_setup()
540 /* Auto Encode w/ Bit 8 = 0 (see LPC MLC Controller manual) */ in lpc32xx_write_page_lowlevel()
554 /* Read whole page - necessary with MLC controller! */ in lpc32xx_read_oob()
562 /* None, write_oob conflicts with the automatic LPC MLC ECC decoder! */ in lpc32xx_write_oob()
566 /* Prepares MLC for transfers with H/W ECC enabled: always enabled anyway */
585 "nand-mlc"); in lpc32xx_dma_setup()
[all …]
DKconfig178 tristate "NXP LPC32xx MLC NAND controller"
182 Uses the LPC32XX MLC (i.e. for Multi Level Cell chips) NAND
187 by the MLC NAND controller.
/kernel/linux/linux-5.10/include/linux/mtd/
Dlpc32xx_mlc.h3 * Platform data for LPC32xx SoC MLC NAND controller
/kernel/linux/linux-6.6/include/linux/mtd/
Dlpc32xx_mlc.h3 * Platform data for LPC32xx SoC MLC NAND controller
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mfd/
Dhi6421.txt24 // supply for MLC NAND/ eMMC
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mfd/
Dhi6421.txt24 // supply for MLC NAND/ eMMC
/kernel/linux/linux-6.6/drivers/video/fbdev/
Dimsttfb.c312 __u8 mlc[3]; /* Memory Loop Config 0x39 */ member
586 __u8 mlc, lckl_p; in set_imstt_regvals_tvp() local
594 mlc = init->mlc[0]; in set_imstt_regvals_tvp()
601 mlc = init->mlc[1]; in set_imstt_regvals_tvp()
608 mlc = init->mlc[2]; in set_imstt_regvals_tvp()
615 mlc = init->mlc[2]; in set_imstt_regvals_tvp()
645 par->cmap_regs[TVPIDATA] = mlc; eieio(); in set_imstt_regvals_tvp()
/kernel/linux/linux-5.10/drivers/video/fbdev/
Dimsttfb.c311 __u8 mlc[3]; /* Memory Loop Config 0x39 */ member
585 __u8 mlc, lckl_p; in set_imstt_regvals_tvp() local
593 mlc = init->mlc[0]; in set_imstt_regvals_tvp()
600 mlc = init->mlc[1]; in set_imstt_regvals_tvp()
607 mlc = init->mlc[2]; in set_imstt_regvals_tvp()
614 mlc = init->mlc[2]; in set_imstt_regvals_tvp()
644 par->cmap_regs[TVPIDATA] = mlc; eieio(); in set_imstt_regvals_tvp()
/kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/lpc/
Dlpc32xx.dtsi63 * Enable either SLC or MLC
72 mlc: flash@200a8000 { label
73 compatible = "nxp,lpc3220-mlc";

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