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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/reset/
Dxlnx,zynqmp-reset.txt2 = Zynq UltraScale+ MPSoC and Versal reset driver binding =
4 The Zynq UltraScale+ MPSoC and Versal has several different resets.
6 See Chapter 36 of the Zynq UltraScale+ MPSoC TRM (UG) for more information
13 - compatible: "xlnx,zynqmp-reset" for Zynq UltraScale+ MPSoC platform
41 For list of all valid reset indices for Zynq UltraScale+ MPSoC see
/kernel/linux/linux-6.6/drivers/firmware/xilinx/
DKconfig4 menu "Zynq MPSoC Firmware Drivers"
8 bool "Enable Xilinx Zynq MPSoC firmware interface"
20 bool "Enable Xilinx Zynq MPSoC firmware debug APIs"
Dzynqmp-debug.h3 * Xilinx Zynq MPSoC Firmware layer
/kernel/linux/linux-5.10/drivers/firmware/xilinx/
DKconfig4 menu "Zynq MPSoC Firmware Drivers"
8 bool "Enable Xilinx Zynq MPSoC firmware interface"
20 bool "Enable Xilinx Zynq MPSoC firmware debug APIs"
Dzynqmp-debug.h3 * Xilinx Zynq MPSoC Firmware layer
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dxlnx,zynqmp-clk.txt2 Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using
3 Zynq MPSoC firmware interface
5 The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock
24 The Zynq UltraScale+ MPSoC has one primary and four alternative reference clock
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/reset/
Dxlnx,zynqmp-reset.yaml7 title: Zynq UltraScale+ MPSoC and Versal reset
13 The Zynq UltraScale+ MPSoC and Versal has several different resets.
24 For list of all valid reset indices for Zynq UltraScale+ MPSoC
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/firmware/xilinx/
Dxlnx,zynqmp-firmware.txt2 Device Tree Bindings for the Xilinx Zynq MPSoC Firmware Interface
15 "xlnx,zynqmp-firmware" for Zynq Ultrascale+ MPSoC
26 Zynq Ultrascale+ MPSoC
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/rtc/
Dxlnx-rtc.txt1 * Xilinx Zynq Ultrascale+ MPSoC Real Time Clock
3 RTC controller for the Xilinx Zynq MPSoC Real Time Clock
/kernel/linux/linux-6.6/drivers/soc/xilinx/
DKconfig5 bool "Enable Xilinx Zynq MPSoC Power Management driver"
20 bool "Enable Zynq MPSoC generic PM domains"
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/fpga/
Dxlnx,zynqmp-pcap-fpga.yaml7 title: Xilinx Zynq Ultrascale MPSoC FPGA Manager
13 Device Tree Bindings for Zynq Ultrascale MPSoC FPGA Manager.
/kernel/linux/linux-5.10/drivers/soc/xilinx/
DKconfig21 bool "Enable Xilinx Zynq MPSoC Power Management driver"
36 bool "Enable Zynq MPSoC generic PM domains"
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/power/
Dxlnx,zynqmp-genpd.txt2 Device Tree Bindings for the Xilinx Zynq MPSoC PM domains
9 == Zynq MPSoC Generic PM Domain Node ==
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/rtc/
Dxlnx,zynqmp-rtc.yaml7 title: Xilinx Zynq Ultrascale+ MPSoC Real Time Clock
10 RTC controller for the Xilinx Zynq MPSoC Real Time Clock.
/kernel/linux/linux-5.10/Documentation/driver-api/xilinx/
Deemi.rst2 Xilinx Zynq MPSoC EEMI Documentation
5 Xilinx Zynq MPSoC Firmware Interface
/kernel/linux/linux-6.6/Documentation/driver-api/xilinx/
Deemi.rst2 Xilinx Zynq MPSoC EEMI Documentation
5 Xilinx Zynq MPSoC Firmware Interface
/kernel/linux/linux-5.10/drivers/clk/zynqmp/
DMakefile2 # Zynq Ultrascale+ MPSoC clock specific Makefile
/kernel/linux/linux-6.6/drivers/clk/zynqmp/
DMakefile2 # Zynq Ultrascale+ MPSoC clock specific Makefile
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/fpga/
Dxlnx,zynqmp-pcap-fpga.txt1 Devicetree bindings for Zynq Ultrascale MPSoC FPGA Manager.
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dcdns,macb.yaml24 - cdns,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
32 - xlnx,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/serial/
Dcdns,uart.txt6 Use "xlnx,zynqmp-uart","cdns,uart-r1p12" for Zynq Ultrascale+ MPSoC.
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/
Dspi-zynqmp-qspi.txt1 Xilinx Zynq UltraScale+ MPSoC GQSPI controller Device Tree Bindings
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/spi/
Dspi-zynqmp-qspi.yaml7 title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/nvmem/
Dxlnx,zynqmp-nvmem.txt2 = Zynq UltraScale+ MPSoC nvmem firmware driver binding =
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/serial/
Dcdns,uart.yaml19 - description: UART controller for Zynq Ultrascale+ MPSoC

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