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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/
Dxilinx-nwl-pcie.txt1 * Xilinx NWL PCIe Root Port Bridge DT description
4 - compatible: Should contain "xlnx,nwl-pcie-2.11"
16 - interrupts: Should contain NWL PCIe interrupt
43 compatible = "xlnx,nwl-pcie-2.11";
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/bridge/
Dnwl-dsi.yaml4 $id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml#
14 NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
15 the SOCs NWL MIPI-DSI host controller.
22 const: fsl,imx8mq-nwl-dsi
177 compatible = "fsl,imx8mq-nwl-dsi";
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/bridge/
Dnwl-dsi.yaml4 $id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml#
14 NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
15 the SOCs NWL MIPI-DSI host controller.
22 const: fsl,imx8mq-nwl-dsi
150 compatible = "fsl,imx8mq-nwl-dsi";
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/
Dxlnx,nwl-pcie.yaml4 $id: http://devicetree.org/schemas/pci/xlnx,nwl-pcie.yaml#
7 title: Xilinx NWL PCIe Root Port Bridge
18 const: xlnx,nwl-pcie-2.11
118 compatible = "xlnx,nwl-pcie-2.11";
/kernel/linux/linux-6.6/drivers/gpu/drm/bridge/
Dnwl-dsi.c3 * i.MX8 NWL MIPI DSI host driver
34 #include "nwl-dsi.h"
36 #define DRV_NAME "nwl-dsi"
38 /* i.MX8 NWL quirks */
77 * The DSI host controller needs this reset sequence according to NWL:
146 "Failed to write NWL DSI reg 0x%x: %d\n", reg, in nwl_dsi_write()
162 DRM_DEV_ERROR(dsi->dev, "Failed to read NWL DSI reg 0x%x: %d\n", in nwl_dsi_read()
787 * dphy and nwl dsi host in nwl_dsi_get_dphy_params()
826 /* At least LCDIF + NWL needs active high sync */ in nwl_dsi_bridge_atomic_check()
1050 DRM_DEV_ERROR(dsi->dev, "Failed to create NWL DSI regmap: %d\n", in nwl_dsi_parse_dt()
[all …]
DMakefile34 obj-$(CONFIG_DRM_NWL_MIPI_DSI) += nwl-dsi.o
Dnwl-dsi.h3 * NWL MIPI DSI host driver
/kernel/linux/linux-5.10/drivers/gpu/drm/bridge/
Dnwl-dsi.c3 * i.MX8 NWL MIPI DSI host driver
33 #include "nwl-dsi.h"
35 #define DRV_NAME "nwl-dsi"
37 /* i.MX8 NWL quirks */
83 * The DSI host controller needs this reset sequence according to NWL:
152 "Failed to write NWL DSI reg 0x%x: %d\n", reg, in nwl_dsi_write()
168 DRM_DEV_ERROR(dsi->dev, "Failed to read NWL DSI reg 0x%x: %d\n", in nwl_dsi_read()
794 * dphy and nwl dsi host in nwl_dsi_get_dphy_params()
833 /* At least LCDIF + NWL needs active high sync */ in nwl_dsi_bridge_atomic_check()
1048 DRM_DEV_ERROR(dsi->dev, "Failed to create NWL DSI regmap: %d\n", in nwl_dsi_parse_dt()
[all …]
DMakefile25 obj-$(CONFIG_DRM_NWL_MIPI_DSI) += nwl-dsi.o
Dnwl-dsi.h3 * NWL MIPI DSI host driver
/kernel/linux/linux-5.10/drivers/pci/controller/
DKconfig26 bool "NWL PCIe Core"
31 NWL PCIe controller. The controller can act as Root Port
DMakefile15 obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o
Dpcie-xilinx-nwl.c3 * PCIe host controller driver for NWL PCIe Bridge
804 { .compatible = "xlnx,nwl-pcie-2.11", },
868 .name = "nwl-pcie",
/kernel/linux/linux-6.6/drivers/pci/controller/
DKconfig328 bool "Xilinx NWL PCIe controller"
333 NWL PCIe controller. The controller can act as Root Port
DMakefile18 obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o
Dpcie-xilinx-nwl.c3 * PCIe host controller driver for NWL PCIe Bridge
777 { .compatible = "xlnx,nwl-pcie-2.11", },
855 .name = "nwl-pcie",
/kernel/linux/linux-6.6/drivers/gpu/drm/imx/dcss/
Ddcss-drv.c50 hdmi_output = !of_device_is_compatible(remote, "fsl,imx8mq-nwl-dsi"); in dcss_drv_platform_probe()
/kernel/linux/linux-5.10/drivers/gpu/drm/imx/dcss/
Ddcss-drv.c48 hdmi_output = !of_device_is_compatible(remote, "fsl,imx8mq-nwl-dsi"); in dcss_drv_platform_probe()
/kernel/linux/linux-5.10/arch/arm64/boot/dts/xilinx/
Dzynqmp.dtsi525 compatible = "xlnx,nwl-pcie-2.11";
/kernel/linux/linux-6.6/arch/arm64/boot/dts/xilinx/
Dzynqmp.dtsi681 compatible = "xlnx,nwl-pcie-2.11";
/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
Dimx8mq.dtsi910 compatible = "fsl,imx8mq-nwl-dsi";
/kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/
Dimx8mq.dtsi1252 compatible = "fsl,imx8mq-nwl-dsi";
/kernel/linux/patches/linux-5.10/imx8mm_patch/patches/drivers/
D0020_linux_drivers_gpu.patch58 @@ -27,3 +27,4 @@ obj-$(CONFIG_DRM_NWL_MIPI_DSI) += nwl-dsi.o
6080 diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-dsi.c
6082 --- a/drivers/gpu/drm/bridge/nwl-dsi.c
6083 +++ b/drivers/gpu/drm/bridge/nwl-dsi.c
6110 #include "nwl-dsi.h"
6201 * The DSI host controller needs this reset sequence according to NWL:
6688 - /* At least LCDIF + NWL needs active high sync */
6729 + /* At least LCDIF + NWL needs active high sync */
7182 + if (of_device_is_compatible(dsi->dev->of_node, "fsl,imx8mq-nwl-dsi"))
7406 - { .compatible = "fsl,imx8mq-nwl-dsi", },
[all …]
/kernel/linux/patches/linux-5.10/imx8mm_patch/patches/
D0001_linux_arch.patch4886 + compatible = "fsl,imx8qx-nwl-dsi";
5048 + compatible = "fsl,imx8qx-nwl-dsi";
/kernel/linux/patches/linux-5.10/yangfan_patch/
Ddrivers.patch11092 diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-dsi.c
11094 --- a/drivers/gpu/drm/bridge/nwl-dsi.c
11095 +++ b/drivers/gpu/drm/bridge/nwl-dsi.c