| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/ |
| D | nvidia,tegra234-mgbe.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra234 MGBE Multi-Gigabit Ethernet Controller
10 - Thierry Reding <treding@nvidia.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra234-mgbe
20 reg-names:
22 - const: hypervisor
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| D | ethernet-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
20 local-mac-address:
23 $ref: /schemas/types.yaml#/definitions/uint8-array
27 mac-address:
32 local-mac-address property.
33 $ref: /schemas/types.yaml#/definitions/uint8-array
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| D | xlnx,axi-ethernet.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 provides connectivity to an external ethernet PHY supporting different
22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
29 - xlnx,axi-ethernet-2.01.a
35 axistream-connected is specified, in which case the reg
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| D | fsl,qoriq-mc-dpmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,qoriq-mc-dpmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ioana Ciornei <ioana.ciornei@nxp.com>
13 This binding represents the DPAA2 MAC objects found on the fsl-mc bus and
14 located under the 'dpmacs' node for the fsl-mc bus DTS node.
17 - $ref: ethernet-controller.yaml#
21 const: fsl,qoriq-mc-dpmac
27 phy-handle: true
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| D | fsl,fman-dtsec.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,fman-dtsec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Madalin Bucur <madalin.bucur@nxp.com>
15 10/100/1000 MBit/s speeds, and the 10-Gigabit Ethernet Media Access Controller
22 - fsl,fman-dtsec
23 - fsl,fman-xgec
24 - fsl,fman-memac
26 cell-index:
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| /kernel/linux/linux-6.6/drivers/phy/qualcomm/ |
| D | phy-qcom-qmp.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
9 #include "phy-qcom-qmp-qserdes-com.h"
10 #include "phy-qcom-qmp-qserdes-txrx.h"
12 #include "phy-qcom-qmp-qserdes-com-v3.h"
13 #include "phy-qcom-qmp-qserdes-txrx-v3.h"
15 #include "phy-qcom-qmp-qserdes-com-v4.h"
16 #include "phy-qcom-qmp-qserdes-txrx-v4.h"
17 #include "phy-qcom-qmp-qserdes-txrx-v4_20.h"
19 #include "phy-qcom-qmp-qserdes-com-v5.h"
20 #include "phy-qcom-qmp-qserdes-txrx-v5.h"
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| D | phy-qcom-qmp-ufs.c | 1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
16 #include <linux/phy/phy.h>
23 #include "phy-qcom-qmp.h"
24 #include "phy-qcom-qmp-pcs-ufs-v2.h"
25 #include "phy-qcom-qmp-pcs-ufs-v3.h"
26 #include "phy-qcom-qmp-pcs-ufs-v4.h"
27 #include "phy-qcom-qmp-pcs-ufs-v5.h"
28 #include "phy-qcom-qmp-pcs-ufs-v6.h"
30 #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"
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| D | phy-qcom-qmp-pcie-msm8996.c | 1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
16 #include <linux/phy/phy.h>
22 #include "phy-qcom-qmp.h"
66 /* set of registers with offsets different per-PHY */
73 /* PCS registers */
169 /* struct qmp_phy_cfg - per-PHY initialization config */
174 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
199 * struct qmp_phy - per-lane phy descriptor
201 * @phy: generic phy
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| D | phy-qcom-qmp-usb-legacy.c | 1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
17 #include <linux/phy/phy.h>
23 #include "phy-qcom-qmp.h"
24 #include "phy-qcom-qmp-pcs-misc-v3.h"
25 #include "phy-qcom-qmp-pcs-usb-v4.h"
26 #include "phy-qcom-qmp-pcs-usb-v5.h"
39 /* DP PHY soft reset */
41 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */
43 /* USB3 PHY soft reset */
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| D | phy-qcom-qmp-pcie.c | 1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
17 #include <linux/phy/pcie.h>
18 #include <linux/phy/phy.h>
25 #include "phy-qcom-qmp.h"
26 #include "phy-qcom-qmp-pcs-misc-v3.h"
27 #include "phy-qcom-qmp-pcs-pcie-v4.h"
28 #include "phy-qcom-qmp-pcs-pcie-v4_20.h"
29 #include "phy-qcom-qmp-pcs-pcie-v5.h"
30 #include "phy-qcom-qmp-pcs-pcie-v5_20.h"
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| D | phy-qcom-qmp-usb.c | 1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
16 #include <linux/phy/phy.h>
22 #include "phy-qcom-qmp.h"
23 #include "phy-qcom-qmp-pcs-misc-v3.h"
24 #include "phy-qcom-qmp-pcs-usb-v4.h"
25 #include "phy-qcom-qmp-pcs-usb-v5.h"
38 /* DP PHY soft reset */
40 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */
42 /* USB3 PHY soft reset */
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| /kernel/linux/linux-6.6/drivers/net/phy/ |
| D | phylink.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * phylink models the MAC to optional PHY connection, supporting
4 * technologies such as SFP cages where the PHY is hot-pluggable.
15 #include <linux/phy.h>
44 * struct phylink - internal data type for phylink
51 struct phylink_pcs *pcs; member
60 u8 link_port; /* The current non-phy ethtool port */
93 if ((pl)->config->type == PHYLINK_NETDEV) \
94 netdev_printk(level, (pl)->netdev, fmt, ##__VA_ARGS__); \
95 else if ((pl)->config->type == PHYLINK_DEV) \
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| /kernel/linux/linux-6.6/include/linux/ |
| D | phylink.h | 4 #include <linux/phy.h>
21 MLO_AN_PHY = 0, /* Conventional PHY */
22 MLO_AN_FIXED, /* Fixed-link mode */
23 MLO_AN_INBAND, /* In-band protocol */
25 /* PCS "negotiation" mode.
26 * PHYLINK_PCS_NEG_NONE - protocol has no inband capability
27 * PHYLINK_PCS_NEG_OUTBAND - some out of band or fixed link setting
28 * PHYLINK_PCS_NEG_INBAND_DISABLED - inband mode disabled, e.g.
29 * 1000base-X with autoneg off
30 * PHYLINK_PCS_NEG_INBAND_ENABLED - inband mode enabled
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/ |
| D | fsl-ls1088a-rdb.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2017-2020 NXP
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
21 phy-handle = <&mdio2_aquantia_phy>;
22 phy-connection-type = "10gbase-r";
23 pcs-handle = <&pcs2>;
27 phy-handle = <&mdio1_phy5>;
28 phy-connection-type = "qsgmii";
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| D | fsl-ls1088a-ten64.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Based on fsl-ls1088a-rdb.dts
5 * Copyright 2017-2020 NXP
6 * Copyright 2019-2021 Traverse Technologies
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
28 stdout-path = "serial0:115200n8";
32 compatible = "gpio-keys";
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| /kernel/linux/linux-5.10/include/linux/ |
| D | phylink.h | 4 #include <linux/phy.h>
20 MLO_AN_PHY = 0, /* Conventional PHY */
21 MLO_AN_FIXED, /* Fixed-link mode */
22 MLO_AN_INBAND, /* In-band protocol */
31 * struct phylink_link_state - link state structure
61 * struct phylink_config - PHYLINK configuration structure
64 * @pcs_poll: MAC PCS cannot provide link change interrupt
80 * struct phylink_mac_ops - MAC operations structure.
108 struct phy_device *phy, unsigned int mode,
113 #if 0 /* For kernel-doc purposes only. */
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| /kernel/linux/linux-5.10/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac-socfpga.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Adopted from dwmac-sti.c
7 #include <linux/mfd/altera-sysmgr.h>
11 #include <linux/phy.h>
54 struct tse_pcs pcs; member
61 void __iomem *splitter_base = dwmac->splitter_base; in socfpga_dwmac_fix_mac_speed()
62 void __iomem *sgmii_adapter_base = dwmac->pcs.sgmii_adapter_base; in socfpga_dwmac_fix_mac_speed()
63 struct device *dev = dwmac->dev; in socfpga_dwmac_fix_mac_speed()
65 struct phy_device *phy_dev = ndev->phydev; in socfpga_dwmac_fix_mac_speed()
95 tse_pcs_fix_mac_speed(&dwmac->pcs, phy_dev, speed); in socfpga_dwmac_fix_mac_speed()
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| /kernel/linux/linux-5.10/drivers/net/phy/ |
| D | phylink.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * phylink models the MAC to optional PHY connection, supporting
4 * technologies such as SFP cages where the PHY is hot-pluggable.
14 #include <linux/phy.h>
38 * struct phylink - internal data type for phylink
46 struct phylink_pcs *pcs; member
55 u8 link_port; /* The current non-phy ethtool port */
84 if ((pl)->config->type == PHYLINK_NETDEV) \
85 netdev_printk(level, (pl)->netdev, fmt, ##__VA_ARGS__); \
86 else if ((pl)->config->type == PHYLINK_DEV) \
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| /kernel/linux/linux-5.10/drivers/net/fddi/skfp/ |
| D | pcmplc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
71 #define GO_STATE(x) (mib->fddiPORTPCMState = (x)|AFLAG)
72 #define ACTIONS_DONE() (mib->fddiPORTPCMState &= ~AFLAG)
113 * PCL-S control register
114 * this register in the PLC-S controls the scrambling parameters
125 * PCL-S control register
126 * this register in the PLC-S controls the scrambling parameters
156 #define PLC_MS(m) ((int)((0x10000L-(m*100000L/2048))))
195 static void pcm_fsm(struct s_smc *smc, struct s_phy *phy, int cmd);
196 static void pc_rcode_actions(struct s_smc *smc, int bit, struct s_phy *phy);
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| /kernel/linux/linux-6.6/drivers/net/fddi/skfp/ |
| D | pcmplc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
67 #define GO_STATE(x) (mib->fddiPORTPCMState = (x)|AFLAG)
68 #define ACTIONS_DONE() (mib->fddiPORTPCMState &= ~AFLAG)
109 * PCL-S control register
110 * this register in the PLC-S controls the scrambling parameters
121 * PCL-S control register
122 * this register in the PLC-S controls the scrambling parameters
152 #define PLC_MS(m) ((int)((0x10000L-(m*100000L/2048))))
191 static void pcm_fsm(struct s_smc *smc, struct s_phy *phy, int cmd);
192 static void pc_rcode_actions(struct s_smc *smc, int bit, struct s_phy *phy);
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| /kernel/linux/linux-6.6/drivers/net/ethernet/microchip/lan966x/ |
| D | lan966x_phylink.c | 1 // SPDX-License-Identifier: GPL-2.0+
7 #include <linux/phy/phy.h>
14 struct lan966x_port *port = netdev_priv(to_net_dev(config->dev)); in lan966x_phylink_mac_select()
16 return &port->phylink_pcs; in lan966x_phylink_mac_select()
29 struct lan966x_port *port = netdev_priv(to_net_dev(config->dev)); in lan966x_phylink_mac_prepare()
33 if (port->serdes) { in lan966x_phylink_mac_prepare()
34 err = phy_set_mode_ext(port->serdes, PHY_MODE_ETHERNET, in lan966x_phylink_mac_prepare()
37 netdev_err(to_net_dev(config->dev), in lan966x_phylink_mac_prepare()
47 struct phy_device *phy, in lan966x_phylink_mac_link_up() argument
53 struct lan966x_port *port = netdev_priv(to_net_dev(config->dev)); in lan966x_phylink_mac_link_up()
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| /kernel/linux/linux-5.10/drivers/phy/qualcomm/ |
| D | phy-qcom-qmp.c | 1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
17 #include <linux/phy/phy.h>
23 #include <dt-bindings/phy/phy.h>
25 #include "phy-qcom-qmp.h"
42 /* DP PHY soft reset */
44 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */
46 /* USB3 PHY soft reset */
48 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
83 * if yes, then offset gives index in the reg-layout
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| /kernel/linux/linux-6.6/drivers/net/dsa/mv88e6xxx/ |
| D | pcs-639x.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Marvell 88E6352 family SERDES PCS support
15 #include "phy.h"
35 err = mdiodev_c45_read(&mpcs->mdio, MDIO_MMD_PHYXS, regnum); in mv88e639x_read()
46 return mdiodev_c45_write(&mpcs->mdio, MDIO_MMD_PHYXS, regnum, val); in mv88e639x_write()
52 return mdiodev_c45_modify(&mpcs->mdio, MDIO_MMD_PHYXS, regnum, mask, in mv88e639x_modify()
59 return mdiodev_c45_modify_changed(&mpcs->mdio, MDIO_MMD_PHYXS, regnum, in mv88e639x_modify_changed()
73 mpcs->mdio.dev.parent = dev; in mv88e639x_pcs_alloc()
74 mpcs->mdio.bus = bus; in mv88e639x_pcs_alloc()
75 mpcs->mdio.addr = addr; in mv88e639x_pcs_alloc()
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| /kernel/linux/linux-6.6/drivers/net/ethernet/freescale/dpaa2/ |
| D | dpaa2-mac.c | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 #include <linux/pcs-lynx.h>
6 #include <linux/phy/phy.h>
9 #include "dpaa2-eth.h"
10 #include "dpaa2-mac.h"
23 if (mac->ver_major == ver_major) in dpaa2_mac_cmp_ver()
24 return mac->ver_minor - ver_minor; in dpaa2_mac_cmp_ver()
25 return mac->ver_major - ver_major; in dpaa2_mac_cmp_ver()
30 mac->features = 0; in dpaa2_mac_detect_features()
34 mac->features |= DPAA2_MAC_FEATURE_PROTOCOL_CHANGE; in dpaa2_mac_detect_features()
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| /kernel/linux/linux-6.6/drivers/net/dsa/b53/ |
| D | b53_serdes.c | 1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Northstar Plus switch SerDes/SGMII PHY main logic
12 #include <linux/phy.h>
20 static inline struct b53_pcs *pcs_to_b53_pcs(struct phylink_pcs *pcs) in pcs_to_b53_pcs() argument
22 return container_of(pcs, struct b53_pcs, pcs); in pcs_to_b53_pcs()
44 if (dev->serdes_lane == lane) in b53_serdes_set_lane()
51 dev->serdes_lane = lane; in b53_serdes_set_lane()
68 static int b53_serdes_config(struct phylink_pcs *pcs, unsigned int neg_mode, in b53_serdes_config() argument
73 struct b53_device *dev = pcs_to_b53_pcs(pcs)->dev; in b53_serdes_config()
74 u8 lane = pcs_to_b53_pcs(pcs)->lane; in b53_serdes_config()
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