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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/
Dl2c2x0.yaml14 PL220/PL310 and variants) based level 2 cache controller. All these various
34 - arm,pl310-cache
37 # DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
38 - bcm,bcm11351-a2-pl310-cache
42 - brcm,bcm11351-a2-pl310-cache
53 # with arm,pl310-cache controller.
55 - const: arm,pl310-cache
109 I/O coherent mode. Valid only when the arm,pl310-cache compatible
157 description: The default behavior of the L220 or PL310 cache
166 description: enable parity checking on the L2 cache (L220 or PL310).
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/cache/
Dl2c2x0.yaml14 PL220/PL310 and variants) based level 2 cache controller. All these various
34 - arm,pl310-cache
37 # DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
38 - bcm,bcm11351-a2-pl310-cache
42 - brcm,bcm11351-a2-pl310-cache
53 # with arm,pl310-cache controller.
55 - const: arm,pl310-cache
109 I/O coherent mode. Valid only when the arm,pl310-cache compatible
157 description: The default behavior of the L220 or PL310 cache
166 description: enable parity checking on the L2 cache (L220 or PL310).
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/arm/
Dvexpress-v2p-ca9.dts165 compatible = "arm,pl310-cache";
225 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
234 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
270 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
277 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
284 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
291 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dvexpress-v2p-ca9.dts165 compatible = "arm,pl310-cache";
225 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
234 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
270 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
277 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
284 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
291 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
Dartpec6.dtsi61 next-level-cache = <&pl310>;
68 next-level-cache = <&pl310>;
133 pl310: cache-controller@faf10000 { label
134 compatible = "arm,pl310-cache";
Dvf610.dtsi14 compatible = "arm,pl310-cache";
/kernel/linux/linux-5.10/arch/arm/mm/
DKconfig980 or PL310 cache controller, but where its use is optional.
1003 of the L220 and PL310 outer cache controllers.
1008 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1010 The PL310 L2 cache controller implements three types of Clean &
1016 is not correctly implemented in PL310 prior to r2p0 (fixed in r2p0)
1020 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1022 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1024 PL310 can handle normal accesses while it is in progress. Under very
1026 PL310 treats a cacheable write transaction during a Clean &
1031 bool "PL310 errata: cache sync operation may be faulty"
[all …]
Dcache-tauros3.h15 * Marvell Tauros3 L2CC is compatible with PL310 r0p0
Dcache-l2x0.c439 * 588369: PL310 R0P0->R1P0, fixed R2P0.
447 * 727915: PL310 R2P0->R3P0, fixed R3P1.
453 * 752271: PL310 R3P0->R3P1-50REL0, fixed R3P2.
458 * 753970: PL310 R3P0, fixed R3P1.
463 * 769419: PL310 R0P0->R3P1, fixed R3P2.
574 /* restore pl310 setup */ in l2c310_configure()
1325 * coherent, and potentially harmful in certain situations (PCIe/PL310
1751 L2C_ID("arm,pl310-cache", of_l2c310_data),
1752 L2C_ID("brcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data),
1757 L2C_ID("bcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data),
[all …]
/kernel/linux/linux-6.6/arch/arm/mm/
DKconfig996 or PL310 cache controller, but where its use is optional.
1019 of the L220 and PL310 outer cache controllers.
1024 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1026 The PL310 L2 cache controller implements three types of Clean &
1032 is not correctly implemented in PL310 prior to r2p0 (fixed in r2p0)
1036 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1038 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1040 PL310 can handle normal accesses while it is in progress. Under very
1042 PL310 treats a cacheable write transaction during a Clean &
1047 bool "PL310 errata: cache sync operation may be faulty"
[all …]
Dcache-tauros3.h15 * Marvell Tauros3 L2CC is compatible with PL310 r0p0
/kernel/linux/linux-5.10/drivers/soc/tegra/
DKconfig22 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
36 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
/kernel/linux/linux-6.6/drivers/soc/tegra/
DKconfig22 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
36 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
/kernel/linux/linux-5.10/arch/arm/mach-mvebu/
Dcoherency.c180 * We should switch the PL310 to I/O coherency mode only if in armada_375_380_coherency_init()
187 * Add the PL310 property "arm,io-coherent". This makes sure the in armada_375_380_coherency_init()
193 for_each_compatible_node(cache_dn, NULL, "arm,pl310-cache") { in armada_375_380_coherency_init()
/kernel/linux/linux-6.6/arch/arm/mach-mvebu/
Dcoherency.c177 * We should switch the PL310 to I/O coherency mode only if in armada_375_380_coherency_init()
184 * Add the PL310 property "arm,io-coherent". This makes sure the in armada_375_380_coherency_init()
190 for_each_compatible_node(cache_dn, NULL, "arm,pl310-cache") { in armada_375_380_coherency_init()
/kernel/linux/linux-6.6/arch/arm/mach-imx/
Dpm-imx6.c157 .pl310_compat = "arm,pl310-cache",
167 .pl310_compat = "arm,pl310-cache",
177 .pl310_compat = "arm,pl310-cache",
187 .pl310_compat = "arm,pl310-cache",
197 .pl310_compat = "arm,pl310-cache",
553 pr_warn("%s: failed to get pl310-cache base %d!\n", in imx6q_suspend_init()
/kernel/linux/linux-5.10/arch/arm/mach-imx/
Dpm-imx6.c155 .pl310_compat = "arm,pl310-cache",
165 .pl310_compat = "arm,pl310-cache",
175 .pl310_compat = "arm,pl310-cache",
185 .pl310_compat = "arm,pl310-cache",
195 .pl310_compat = "arm,pl310-cache",
551 pr_warn("%s: failed to get pl310-cache base %d!\n", in imx6q_suspend_init()
/kernel/linux/linux-6.6/arch/arm/mach-ux500/
Dcpu-db8500.c35 np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache"); in ux500_l2x0_unlock()
45 * already enabled, so we do it right here instead. The PL310 has in ux500_l2x0_unlock()
/kernel/linux/linux-6.6/arch/arm/boot/dts/axis/
Dartpec6.dtsi61 next-level-cache = <&pl310>;
68 next-level-cache = <&pl310>;
133 pl310: cache-controller@faf10000 { label
134 compatible = "arm,pl310-cache";
/kernel/linux/linux-5.10/arch/arm/mach-ux500/
Dcpu-db8500.c38 np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache"); in ux500_l2x0_unlock()
48 * already enabled, so we do it right here instead. The PL310 has in ux500_l2x0_unlock()
/kernel/linux/linux-5.10/arch/arm/mach-tango/
DKconfig5 # Cortex-A9 MPCore r3p0, PL310 r3p2
/kernel/linux/linux-5.10/arch/arm/mach-socfpga/
DKconfig20 select PL310_ERRATA_753970 if PL310
/kernel/linux/linux-6.6/arch/arm/mach-socfpga/
DKconfig19 select PL310_ERRATA_753970 if PL310
/kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/vf/
Dvf610.dtsi13 compatible = "arm,pl310-cache";
/kernel/linux/linux-6.6/arch/arm/mach-berlin/
Dberlin.c22 * Note: 88DE3005 (Armada 1500-mini) uses pl310 l2cc

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