| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/ |
| D | sifive,plic-1.0.0.yaml | 5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
26 with priority below this threshold will not cause the PLIC to raise its
29 The PLIC supports both edge-triggered and level-triggered interrupts. For
30 edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges
31 seen while an interrupt handler is active; the PLIC may either queue them or
36 RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.
38 While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
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| D | riscv,cpu-intc.txt | 16 via the platform-level interrupt controller (PLIC).
21 entry, though external interrupt controllers (like the PLIC, for example) will
23 a PLIC interrupt property will typically list the HLICs for all present HARTs
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | sifive,plic-1.0.0.yaml | 5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
12 (PLIC) high-level specification in the RISC-V Privileged Architecture
13 specification. The PLIC connects all external interrupts in the system to all
25 with priority below this threshold will not cause the PLIC to raise its
28 While the PLIC supports both edge-triggered and level-triggered interrupts,
30 specified in the PLIC device-tree binding.
32 While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
33 "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
45 - const: sifive,fu540-c000-plic
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| D | riscv,cpu-intc.txt | 16 via the platform-level interrupt controller (PLIC).
21 entry, though external interrupt controllers (like the PLIC, for example) will
23 a PLIC interrupt property will typically list the HLICs for all present HARTs
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| /kernel/linux/linux-6.6/arch/riscv/boot/dts/microchip/ |
| D | mpfs.dtsi | 195 interrupt-parent = <&plic>;
209 plic: interrupt-controller@c000000 { label
210 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
226 interrupt-parent = <&plic>;
277 interrupt-parent = <&plic>;
289 interrupt-parent = <&plic>;
301 interrupt-parent = <&plic>;
313 interrupt-parent = <&plic>;
325 interrupt-parent = <&plic>;
336 interrupt-parent = <&plic>;
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| D | mpfs-icicle-kit-fabric.dtsi | 23 interrupt-parent = <&plic>;
38 interrupt-parent = <&plic>;
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| D | mpfs-m100pfs-fabric.dtsi | 26 interrupt-parent = <&plic>;
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| D | mpfs-polarberry-fabric.dtsi | 26 interrupt-parent = <&plic>;
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| /kernel/linux/linux-6.6/arch/riscv/boot/dts/allwinner/ |
| D | sun20i-d1s.dtsi | 53 interrupt-parent = <&plic>;
63 plic: interrupt-controller@10000000 { label
64 compatible = "allwinner,sun20i-d1-plic",
65 "thead,c900-plic";
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| /kernel/linux/linux-5.10/drivers/irqchip/ |
| D | irq-sifive-plic.c | 6 #define pr_fmt(fmt) "plic: " fmt
23 * This driver implements a version of the RISC-V PLIC with the actual layout
28 * The largest number supported by devices marked as 'sifive,plic-1.0.0', is
176 .name = "SiFive PLIC",
379 * We can have multiple PLIC instances so setup cpuhp state only in plic_init()
385 "irqchip/sifive/plic:starting", in plic_init()
401 IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init);
403 IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_init); /* for firmware driver */
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| D | Kconfig | 533 This enables support for the PLIC chip found in SiFive (and
534 potentially other) RISC-V systems. The PLIC controls devices
537 interrupt sources are subordinate to the PLIC.
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| /kernel/linux/linux-6.6/arch/riscv/boot/dts/renesas/ |
| D | r9a07g043f.dtsi | 45 interrupt-parent = <&plic>;
47 plic: interrupt-controller@12c00000 { label
48 compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
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| /kernel/linux/linux-6.6/drivers/irqchip/ |
| D | irq-sifive-plic.c | 6 #define pr_fmt(fmt) "plic: " fmt
24 * This driver implements a version of the RISC-V PLIC with the actual layout
29 * The largest number supported by devices marked as 'sifive,plic-1.0.0', is
191 .name = "SiFive PLIC",
206 .name = "SiFive PLIC",
542 * We can have multiple PLIC instances so setup cpuhp state in __plic_init()
549 "irqchip/sifive/plic:starting", in __plic_init()
579 IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init);
589 IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_edge_init);
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| D | irq-riscv-intc.c | 82 * (such as PLIC, SBI IPI, CLINT, APLIC, IMSIC, etc) implement in riscv_intc_irq_eoi()
210 * interrupt controllers (such as PLIC, IMSIC and APLIC in riscv_intc_init()
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| /kernel/linux/linux-6.6/arch/riscv/boot/dts/starfive/ |
| D | jh7100.dtsi | 138 interrupt-parent = <&plic>;
150 plic: interrupt-controller@c000000 { label
151 compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
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| /kernel/linux/linux-6.6/arch/riscv/boot/dts/thead/ |
| D | th1520.dtsi | 139 interrupt-parent = <&plic>;
145 plic: interrupt-controller@ffd8000000 { label
146 compatible = "thead,th1520-plic", "thead,c900-plic";
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/can/ |
| D | microchip,mpfs-can.yaml | 43 interrupt-parent = <&plic>;
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/usb/ |
| D | microchip,mpfs-musb.yaml | 53 interrupt-parent = <&plic>;
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/spi/ |
| D | microchip,mpfs-spi.yaml | 55 interrupt-parent = <&plic>;
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/i2c/ |
| D | microchip,corei2c.yaml | 52 interrupt-parent = <&plic>;
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/gpio/ |
| D | sifive,gpio.yaml | 58 interrupt-parent = <&plic>;
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| /kernel/linux/linux-6.6/arch/m68k/include/asm/ |
| D | m5272sim.h | 110 #define MCF_IRQ_PLIP 75 /* PLIC 2Khz Periodic */
111 #define MCF_IRQ_PLIA 76 /* PLIC Asynchronous */
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| /kernel/linux/linux-5.10/arch/m68k/include/asm/ |
| D | m5272sim.h | 110 #define MCF_IRQ_PLIP 75 /* PLIC 2Khz Periodic */
111 #define MCF_IRQ_PLIA 76 /* PLIC Asynchronous */
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pwm/ |
| D | pwm-sifive.yaml | 69 interrupt-parent = <&plic>;
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pwm/ |
| D | pwm-sifive.yaml | 66 interrupt-parent = <&plic>;
|