| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/ |
| D | intel_cx0_phy.c | 422 * registers 0xC04 to 0xC08(pll[4] to pll[8]) will be
430 .pll[0] = 0xB4,
431 .pll[1] = 0,
432 .pll[2] = 0x30,
433 .pll[3] = 0x1,
434 .pll[4] = 0x26,
435 .pll[5] = 0x0C,
436 .pll[6] = 0x98,
437 .pll[7] = 0x46,
438 .pll[8] = 0x1,
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/mediatek/ |
| D | clk-pll.c | 16 #include "clk-pll.h"
35 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); in mtk_pll_is_prepared() local
37 return (readl(pll->en_addr) & BIT(pll->data->pll_en_bit)) != 0; in mtk_pll_is_prepared()
40 static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, in __mtk_pll_recalc_rate() argument
43 int pcwbits = pll->data->pcwbits; in __mtk_pll_recalc_rate()
49 /* The fractional part of the PLL divider. */ in __mtk_pll_recalc_rate()
50 ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS; in __mtk_pll_recalc_rate()
67 static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll) in __mtk_pll_tuner_enable() argument
71 if (pll->tuner_en_addr) { in __mtk_pll_tuner_enable()
72 r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit); in __mtk_pll_tuner_enable()
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/qcom/ |
| D | clk-alpha-pll.c | 13 #include "clk-alpha-pll.h"
282 /* TRION PLL specific settings and offsets */
286 /* LUCID PLL specific settings and offsets */
289 /* LUCID 5LPE PLL specific settings and offsets */
295 /* LUCID EVO PLL specific settings and offsets */
301 /* ZONDA PLL specific */
318 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, in wait_for_pll() argument
324 const char *name = clk_hw_get_name(&pll->clkr.hw); in wait_for_pll()
326 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in wait_for_pll()
331 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in wait_for_pll()
[all …]
|
| D | clk-pll.c | 17 #include "clk-pll.h"
26 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable() local
31 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable()
39 /* Disable PLL bypass mode. */ in clk_pll_enable()
40 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
51 /* De-assert active-low PLL reset. */ in clk_pll_enable()
52 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, in clk_pll_enable()
57 /* Wait until PLL is locked. */ in clk_pll_enable()
60 /* Enable PLL output. */ in clk_pll_enable()
61 return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL, in clk_pll_enable()
[all …]
|
| /kernel/linux/linux-5.10/drivers/clk/tegra/ |
| D | clk-pll.c | 276 static void clk_pll_enable_lock(struct tegra_clk_pll *pll) in clk_pll_enable_lock() argument
280 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) in clk_pll_enable_lock()
283 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE)) in clk_pll_enable_lock()
286 val = pll_readl_misc(pll); in clk_pll_enable_lock()
287 val |= BIT(pll->params->lock_enable_bit_idx); in clk_pll_enable_lock()
288 pll_writel_misc(val, pll); in clk_pll_enable_lock()
291 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll) in clk_pll_wait_for_lock() argument
297 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) { in clk_pll_wait_for_lock()
298 udelay(pll->params->lock_delay); in clk_pll_wait_for_lock()
302 lock_addr = pll->clk_base; in clk_pll_wait_for_lock()
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/tegra/ |
| D | clk-pll.c | 276 static void clk_pll_enable_lock(struct tegra_clk_pll *pll) in clk_pll_enable_lock() argument
280 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) in clk_pll_enable_lock()
283 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE)) in clk_pll_enable_lock()
286 val = pll_readl_misc(pll); in clk_pll_enable_lock()
287 val |= BIT(pll->params->lock_enable_bit_idx); in clk_pll_enable_lock()
288 pll_writel_misc(val, pll); in clk_pll_enable_lock()
291 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll) in clk_pll_wait_for_lock() argument
297 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) { in clk_pll_wait_for_lock()
298 udelay(pll->params->lock_delay); in clk_pll_wait_for_lock()
302 lock_addr = pll->clk_base; in clk_pll_wait_for_lock()
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/dsi/pll/ |
| D | dsi_pll.c | 8 static int dsi_pll_enable(struct msm_dsi_pll *pll) in dsi_pll_enable() argument
16 if (unlikely(pll->pll_on)) in dsi_pll_enable()
20 for (i = 0; i < pll->en_seq_cnt; i++) { in dsi_pll_enable()
21 ret = pll->enable_seqs[i](pll); in dsi_pll_enable()
22 DBG("DSI PLL %s after sequence #%d", in dsi_pll_enable()
29 DRM_ERROR("DSI PLL failed to lock\n"); in dsi_pll_enable()
33 pll->pll_on = true; in dsi_pll_enable()
38 static void dsi_pll_disable(struct msm_dsi_pll *pll) in dsi_pll_disable() argument
40 if (unlikely(!pll->pll_on)) in dsi_pll_disable()
43 pll->disable_seq(pll); in dsi_pll_disable()
[all …]
|
| /kernel/linux/linux-5.10/drivers/clk/mediatek/ |
| D | clk-pll.c | 33 * a divider in the PLL feedback loop which consists of 7 bits for the integer
57 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); in mtk_pll_is_prepared() local
59 return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0; in mtk_pll_is_prepared()
62 static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, in __mtk_pll_recalc_rate() argument
65 int pcwbits = pll->data->pcwbits; in __mtk_pll_recalc_rate()
71 /* The fractional part of the PLL divider. */ in __mtk_pll_recalc_rate()
72 ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS; in __mtk_pll_recalc_rate()
89 static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll) in __mtk_pll_tuner_enable() argument
93 if (pll->tuner_en_addr) { in __mtk_pll_tuner_enable()
94 r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit); in __mtk_pll_tuner_enable()
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/sprd/ |
| D | pll.c | 3 // Spreadtrum pll clock driver
13 #include "pll.h"
18 #define pindex(pll, member) \ argument
19 (pll->factors[member].shift / (8 * sizeof(pll->regs_num)))
21 #define pshift(pll, member) \ argument
22 (pll->factors[member].shift % (8 * sizeof(pll->regs_num)))
24 #define pwidth(pll, member) \ argument
25 pll->factors[member].width
27 #define pmask(pll, member) \ argument
28 ((pwidth(pll, member)) ? \
[all …]
|
| /kernel/linux/linux-5.10/drivers/clk/sprd/ |
| D | pll.c | 3 // Spreadtrum pll clock driver
13 #include "pll.h"
18 #define pindex(pll, member) \ argument
19 (pll->factors[member].shift / (8 * sizeof(pll->regs_num)))
21 #define pshift(pll, member) \ argument
22 (pll->factors[member].shift % (8 * sizeof(pll->regs_num)))
24 #define pwidth(pll, member) \ argument
25 pll->factors[member].width
27 #define pmask(pll, member) \ argument
28 ((pwidth(pll, member)) ? \
[all …]
|
| /kernel/linux/linux-5.10/drivers/clk/qcom/ |
| D | clk-alpha-pll.c | 12 #include "clk-alpha-pll.h"
142 /* TRION PLL specific settings and offsets */
146 /* LUCID PLL specific settings and offsets */
161 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, in wait_for_pll() argument
167 const char *name = clk_hw_get_name(&pll->clkr.hw); in wait_for_pll()
169 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in wait_for_pll()
174 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in wait_for_pll()
189 #define wait_for_pll_enable_active(pll) \ argument
190 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable")
192 #define wait_for_pll_enable_lock(pll) \ argument
[all …]
|
| D | clk-pll.c | 17 #include "clk-pll.h"
26 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable() local
31 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable()
39 /* Disable PLL bypass mode. */ in clk_pll_enable()
40 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
51 /* De-assert active-low PLL reset. */ in clk_pll_enable()
52 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, in clk_pll_enable()
57 /* Wait until PLL is locked. */ in clk_pll_enable()
60 /* Enable PLL output. */ in clk_pll_enable()
61 return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL, in clk_pll_enable()
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/imx/ |
| D | clk-pllv3.c | 33 * struct clk_pllv3 - IMX PLL clock version 3
35 * @base: base address of PLL registers
36 * @power_bit: pll power bit mask
37 * @powerup_set: set power_bit to power up the PLL
44 * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3
61 static int clk_pllv3_wait_lock(struct clk_pllv3 *pll) in clk_pllv3_wait_lock() argument
63 u32 val = readl_relaxed(pll->base) & pll->power_bit; in clk_pllv3_wait_lock()
65 /* No need to wait for lock when pll is not powered up */ in clk_pllv3_wait_lock()
66 if ((pll->powerup_set && !val) || (!pll->powerup_set && val)) in clk_pllv3_wait_lock()
69 return readl_relaxed_poll_timeout(pll->base, val, val & BM_PLL_LOCK, in clk_pllv3_wait_lock()
[all …]
|
| /kernel/linux/linux-5.10/drivers/clk/imx/ |
| D | clk-pllv3.c | 32 * struct clk_pllv3 - IMX PLL clock version 3
34 * @base: base address of PLL registers
35 * @power_bit: pll power bit mask
36 * @powerup_set: set power_bit to power up the PLL
43 * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3
60 static int clk_pllv3_wait_lock(struct clk_pllv3 *pll) in clk_pllv3_wait_lock() argument
62 u32 val = readl_relaxed(pll->base) & pll->power_bit; in clk_pllv3_wait_lock()
64 /* No need to wait for lock when pll is not powered up */ in clk_pllv3_wait_lock()
65 if ((pll->powerup_set && !val) || (!pll->powerup_set && val)) in clk_pllv3_wait_lock()
68 return readl_relaxed_poll_timeout(pll->base, val, val & BM_PLL_LOCK, in clk_pllv3_wait_lock()
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/meson/ |
| D | clk-pll.c | 11 * In the most basic form, a Meson PLL is composed as follows:
13 * PLL
37 #include "clk-pll.h"
45 static int __pll_round_closest_mult(struct meson_clk_pll_data *pll) in __pll_round_closest_mult() argument
47 if ((pll->flags & CLK_MESON_PLL_ROUND_CLOSEST) && in __pll_round_closest_mult()
48 !MESON_PARM_APPLICABLE(&pll->frac)) in __pll_round_closest_mult()
57 struct meson_clk_pll_data *pll) in __pll_params_to_rate() argument
61 if (frac && MESON_PARM_APPLICABLE(&pll->frac)) { in __pll_params_to_rate()
65 (1 << pll->frac.width)); in __pll_params_to_rate()
75 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); in meson_clk_pll_recalc_rate() local
[all …]
|
| /kernel/linux/linux-5.10/drivers/clk/bcm/ |
| D | clk-iproc-pll.c | 29 * PLL MACRO_SELECT modes 0 to 5 choose pre-calculated PLL output frequencies
30 * from a look-up table. Mode 7 allows user to manipulate PLL clock dividers
34 /* number of delay loops waiting for PLL to lock */
85 struct iproc_pll *pll; member
128 static int pll_get_rate_index(struct iproc_pll *pll, unsigned int target_rate) in pll_get_rate_index() argument
132 for (i = 0; i < pll->num_vco_entries; i++) in pll_get_rate_index()
133 if (target_rate == pll->vco_param[i].rate) in pll_get_rate_index()
136 if (i >= pll->num_vco_entries) in pll_get_rate_index()
157 static int pll_wait_for_lock(struct iproc_pll *pll) in pll_wait_for_lock() argument
160 const struct iproc_pll_ctrl *ctrl = pll->ctrl; in pll_wait_for_lock()
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/bcm/ |
| D | clk-iproc-pll.c | 19 * PLL MACRO_SELECT modes 0 to 5 choose pre-calculated PLL output frequencies
20 * from a look-up table. Mode 7 allows user to manipulate PLL clock dividers
24 /* number of delay loops waiting for PLL to lock */
75 struct iproc_pll *pll; member
118 static int pll_get_rate_index(struct iproc_pll *pll, unsigned int target_rate) in pll_get_rate_index() argument
122 for (i = 0; i < pll->num_vco_entries; i++) in pll_get_rate_index()
123 if (target_rate == pll->vco_param[i].rate) in pll_get_rate_index()
126 if (i >= pll->num_vco_entries) in pll_get_rate_index()
147 static int pll_wait_for_lock(struct iproc_pll *pll) in pll_wait_for_lock() argument
150 const struct iproc_pll_ctrl *ctrl = pll->ctrl; in pll_wait_for_lock()
[all …]
|
| /kernel/linux/linux-6.6/drivers/media/i2c/ |
| D | ccs-pll.c | 3 * drivers/media/i2c/ccs-pll.c
5 * Generic MIPI CCS/SMIA/SMIA++ PLL calculator
17 #include "ccs-pll.h"
78 static void print_pll(struct device *dev, struct ccs_pll *pll) in print_pll() argument
85 { &pll->vt_fr, &pll->vt_bk, PLL_VT }, in print_pll()
86 { &pll->op_fr, &pll->op_bk, PLL_OP } in print_pll()
90 dev_dbg(dev, "ext_clk_freq_hz\t\t%u\n", pll->ext_clk_freq_hz); in print_pll()
95 if (pll->flags & CCS_PLL_FLAG_DUAL_PLL || in print_pll()
108 if (!(pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) || in print_pll()
123 pll->pixel_rate_pixel_array); in print_pll()
[all …]
|
| /kernel/linux/linux-5.10/drivers/media/i2c/ |
| D | smiapp-pll.c | 3 * drivers/media/i2c/smiapp-pll.c
16 #include "smiapp-pll.h"
53 static void print_pll(struct device *dev, struct smiapp_pll *pll) in print_pll() argument
55 dev_dbg(dev, "pre_pll_clk_div\t%u\n", pll->pre_pll_clk_div); in print_pll()
56 dev_dbg(dev, "pll_multiplier \t%u\n", pll->pll_multiplier); in print_pll()
57 if (!(pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)) { in print_pll()
58 dev_dbg(dev, "op_sys_clk_div \t%u\n", pll->op.sys_clk_div); in print_pll()
59 dev_dbg(dev, "op_pix_clk_div \t%u\n", pll->op.pix_clk_div); in print_pll()
61 dev_dbg(dev, "vt_sys_clk_div \t%u\n", pll->vt.sys_clk_div); in print_pll()
62 dev_dbg(dev, "vt_pix_clk_div \t%u\n", pll->vt.pix_clk_div); in print_pll()
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/rockchip/ |
| D | clk-pll.c | 51 struct rockchip_clk_pll *pll, unsigned long rate) in rockchip_get_pll_settings() argument
53 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_get_pll_settings()
56 for (i = 0; i < pll->rate_count; i++) { in rockchip_get_pll_settings()
67 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_pll_round_rate() local
68 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_pll_round_rate()
72 for (i = 0; i < pll->rate_count; i++) { in rockchip_pll_round_rate()
82 * Wait for the pll to reach the locked state.
86 static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll) in rockchip_pll_wait_lock() argument
88 struct regmap *grf = pll->ctx->grf; in rockchip_pll_wait_lock()
92 ret = regmap_read_poll_timeout(grf, pll->lock_offset, val, in rockchip_pll_wait_lock()
[all …]
|
| /kernel/linux/linux-6.6/drivers/video/fbdev/aty/ |
| D | mach64_ct.c | 18 static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll);
19 static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll);
20 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll);
21 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll);
103 * PLL programming (Mach64 CT family)
118 static int aty_dsp_gt(const struct fb_info *info, u32 bpp, struct pll_ct *pll) in aty_dsp_gt() argument
125 multiplier = ((u32)pll->mclk_fb_div) * pll->vclk_post_div_real; in aty_dsp_gt()
126 divider = ((u32)pll->vclk_fb_div) * pll->xclk_ref_div; in aty_dsp_gt()
128 ras_multiplier = pll->xclkmaxrasdelay; in aty_dsp_gt()
134 vshift = (6 - 2) - pll->xclk_post_div; /* FIFO is 64 bits wide in accelerator mode ... */ in aty_dsp_gt()
[all …]
|
| /kernel/linux/linux-5.10/drivers/video/fbdev/aty/ |
| D | mach64_ct.c | 18 static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll);
19 static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll);
20 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll);
21 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll);
105 * PLL programming (Mach64 CT family)
120 static int aty_dsp_gt(const struct fb_info *info, u32 bpp, struct pll_ct *pll) in aty_dsp_gt() argument
127 multiplier = ((u32)pll->mclk_fb_div) * pll->vclk_post_div_real; in aty_dsp_gt()
128 divider = ((u32)pll->vclk_fb_div) * pll->xclk_ref_div; in aty_dsp_gt()
130 ras_multiplier = pll->xclkmaxrasdelay; in aty_dsp_gt()
136 vshift = (6 - 2) - pll->xclk_post_div; /* FIFO is 64 bits wide in accelerator mode ... */ in aty_dsp_gt()
[all …]
|
| /kernel/linux/linux-5.10/drivers/clk/meson/ |
| D | clk-pll.c | 11 * In the most basic form, a Meson PLL is composed as follows:
13 * PLL
38 #include "clk-pll.h"
46 static int __pll_round_closest_mult(struct meson_clk_pll_data *pll) in __pll_round_closest_mult() argument
48 if ((pll->flags & CLK_MESON_PLL_ROUND_CLOSEST) && in __pll_round_closest_mult()
49 !MESON_PARM_APPLICABLE(&pll->frac)) in __pll_round_closest_mult()
58 struct meson_clk_pll_data *pll) in __pll_params_to_rate() argument
62 if (frac && MESON_PARM_APPLICABLE(&pll->frac)) { in __pll_params_to_rate()
66 (1 << pll->frac.width)); in __pll_params_to_rate()
76 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); in meson_clk_pll_recalc_rate() local
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/samsung/ |
| D | clk-pll.c | 6 * This file contains the utility functions to register the pll clocks.
18 #include "clk-pll.h"
27 /* PLL enable control bit offset in @con_reg register */
29 /* PLL lock status bit offset in @con_reg register */
39 struct samsung_clk_pll *pll, unsigned long rate) in samsung_get_pll_settings() argument
41 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_get_pll_settings()
44 for (i = 0; i < pll->rate_count; i++) { in samsung_get_pll_settings()
55 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll_round_rate() local
56 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_pll_round_rate()
60 for (i = 0; i < pll->rate_count; i++) { in samsung_pll_round_rate()
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/visconti/ |
| D | pll.c | 3 * Toshiba Visconti PLL driver
17 #include "pll.h"
56 static void visconti_pll_get_params(struct visconti_pll *pll, in visconti_pll_get_params() argument
61 val = readl(pll->pll_base + PLL_FRACMODE_REG); in visconti_pll_get_params()
66 rate_table->fracin = readl(pll->pll_base + PLL_FRACIN_REG) & PLL_FRACIN_MASK; in visconti_pll_get_params()
67 rate_table->intin = readl(pll->pll_base + PLL_INTIN_REG) & PLL_INTIN_MASK; in visconti_pll_get_params()
68 rate_table->refdiv = readl(pll->pll_base + PLL_REFDIV_REG) & PLL_REFDIV_MASK; in visconti_pll_get_params()
70 postdiv = readl(pll->pll_base + PLL_POSTDIV_REG); in visconti_pll_get_params()
75 static const struct visconti_pll_rate_table *visconti_get_pll_settings(struct visconti_pll *pll, in visconti_get_pll_settings() argument
78 const struct visconti_pll_rate_table *rate_table = pll->rate_table; in visconti_get_pll_settings()
[all …]
|