| /kernel/linux/linux-6.6/drivers/crypto/hisilicon/ |
| D | qm.c | 364 struct hisi_qm *qm; member
380 int (*get_vft)(struct hisi_qm *qm, u32 *base, u32 *number);
381 void (*qm_db)(struct hisi_qm *qm, u16 qn,
383 int (*debug_init)(struct hisi_qm *qm);
384 void (*hw_error_init)(struct hisi_qm *qm);
385 void (*hw_error_uninit)(struct hisi_qm *qm);
386 enum acc_err_result (*hw_error_handle)(struct hisi_qm *qm);
387 int (*set_msi)(struct hisi_qm *qm, bool set);
451 static void qm_irqs_unregister(struct hisi_qm *qm);
452 static int qm_reset_device(struct hisi_qm *qm);
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| D | debugfs.c | 42 int (*dump_fn)(struct hisi_qm *qm, char *cmd, char *info_name);
86 /* define the QM's dfx regs region and region length */
122 static void dump_show(struct hisi_qm *qm, void *info, in dump_show() argument
125 struct device *dev = &qm->pdev->dev; in dump_show()
137 static int qm_sqc_dump(struct hisi_qm *qm, char *s, char *name) in qm_sqc_dump() argument
139 struct device *dev = &qm->pdev->dev; in qm_sqc_dump()
149 if (ret || qp_id >= qm->qp_num) { in qm_sqc_dump()
150 dev_err(dev, "Please input qp num (0-%u)", qm->qp_num - 1); in qm_sqc_dump()
154 sqc = hisi_qm_ctx_alloc(qm, sizeof(*sqc), &sqc_dma); in qm_sqc_dump()
158 ret = hisi_qm_mb(qm, QM_MB_CMD_SQC, sqc_dma, qp_id, 1); in qm_sqc_dump()
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| D | qm_common.h | 79 void *hisi_qm_ctx_alloc(struct hisi_qm *qm, size_t ctx_size,
81 void hisi_qm_ctx_free(struct hisi_qm *qm, size_t ctx_size,
83 void hisi_qm_show_last_dfx_regs(struct hisi_qm *qm);
84 void hisi_qm_set_algqos_init(struct hisi_qm *qm);
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| /kernel/linux/linux-5.10/drivers/crypto/hisilicon/ |
| D | qm.c | 18 #include "qm.h"
318 struct hisi_qm *qm; member
324 int (*get_vft)(struct hisi_qm *qm, u32 *base, u32 *number);
325 void (*qm_db)(struct hisi_qm *qm, u16 qn,
327 u32 (*get_irq_num)(struct hisi_qm *qm);
328 int (*debug_init)(struct hisi_qm *qm);
329 void (*hw_error_init)(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe);
330 void (*hw_error_uninit)(struct hisi_qm *qm);
331 enum acc_err_result (*hw_error_handle)(struct hisi_qm *qm);
390 static bool qm_avail_state(struct hisi_qm *qm, enum qm_state new) in qm_avail_state() argument
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| D | qm.h | 15 /* qm user domain */
36 /* qm cache */
182 int (*hw_init)(struct hisi_qm *qm);
183 void (*hw_err_enable)(struct hisi_qm *qm);
184 void (*hw_err_disable)(struct hisi_qm *qm);
185 u32 (*get_dev_hw_err_status)(struct hisi_qm *qm);
186 void (*clear_dev_hw_err_status)(struct hisi_qm *qm, u32 err_sts);
187 void (*open_axi_master_ooo)(struct hisi_qm *qm);
188 void (*close_axi_master_ooo)(struct hisi_qm *qm);
189 void (*log_dev_hw_err)(struct hisi_qm *qm, u32 err_sts);
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| /kernel/linux/linux-6.6/drivers/crypto/hisilicon/sec2/ |
| D | sec_main.c | 306 struct hisi_qm *qm = s->private; in sec_diff_regs_show() local
308 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs, in sec_diff_regs_show()
394 u64 sec_get_alg_bitmap(struct hisi_qm *qm, u32 high, u32 low) in sec_get_alg_bitmap() argument
398 cap_val_h = qm->cap_tables.dev_cap_table[high].cap_val; in sec_get_alg_bitmap()
399 cap_val_l = qm->cap_tables.dev_cap_table[low].cap_val; in sec_get_alg_bitmap()
424 static void sec_set_endian(struct hisi_qm *qm) in sec_set_endian() argument
428 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_set_endian()
436 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); in sec_set_endian()
439 static void sec_engine_sva_config(struct hisi_qm *qm) in sec_engine_sva_config() argument
443 if (qm->ver > QM_HW_V2) { in sec_engine_sva_config()
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| D | sec.h | 168 struct hisi_qm *qm; member
187 struct hisi_qm qm; member
230 int sec_register_to_crypto(struct hisi_qm *qm);
231 void sec_unregister_from_crypto(struct hisi_qm *qm);
232 u64 sec_get_alg_bitmap(struct hisi_qm *qm, u32 high, u32 low);
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| /kernel/linux/linux-5.10/drivers/crypto/hisilicon/sec2/ |
| D | sec_main.c | 87 #define SEC_ADDR(qm, offset) ((qm)->io_base + (offset) + \ argument
244 static u8 sec_get_endian(struct hisi_qm *qm) in sec_get_endian() argument
252 if (qm->pdev->is_virtfn) { in sec_get_endian()
253 dev_err_ratelimited(&qm->pdev->dev, in sec_get_endian()
257 reg = readl_relaxed(qm->io_base + SEC_ENGINE_PF_CFG_OFF + in sec_get_endian()
273 static int sec_engine_init(struct hisi_qm *qm) in sec_engine_init() argument
279 reg = readl_relaxed(SEC_ADDR(qm, SEC_CONTROL_REG)); in sec_engine_init()
281 writel_relaxed(reg, SEC_ADDR(qm, SEC_CONTROL_REG)); in sec_engine_init()
283 writel_relaxed(0x1, SEC_ADDR(qm, SEC_MEM_START_INIT_REG)); in sec_engine_init()
285 ret = readl_relaxed_poll_timeout(SEC_ADDR(qm, SEC_MEM_INIT_DONE_REG), in sec_engine_init()
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| /kernel/linux/linux-6.6/drivers/crypto/hisilicon/hpre/ |
| D | hpre_main.c | 358 bool hpre_check_alg_support(struct hisi_qm *qm, u32 alg) in hpre_check_alg_support() argument
362 cap_val = qm->cap_tables.dev_cap_table[HPRE_DRV_ALG_BITMAP_CAP_IDX].cap_val; in hpre_check_alg_support()
371 struct hisi_qm *qm = s->private; in hpre_diff_regs_show() local
373 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs, in hpre_diff_regs_show()
458 static void hpre_config_pasid(struct hisi_qm *qm) in hpre_config_pasid() argument
462 if (qm->ver >= QM_HW_V3) in hpre_config_pasid()
465 val1 = readl_relaxed(qm->io_base + HPRE_DATA_RUSER_CFG); in hpre_config_pasid()
466 val2 = readl_relaxed(qm->io_base + HPRE_DATA_WUSER_CFG); in hpre_config_pasid()
467 if (qm->use_sva) { in hpre_config_pasid()
474 writel_relaxed(val1, qm->io_base + HPRE_DATA_RUSER_CFG); in hpre_config_pasid()
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| D | hpre.h | 14 * type used in qm sqc DW6.
71 struct hisi_qm qm; member
104 int hpre_algs_register(struct hisi_qm *qm);
105 void hpre_algs_unregister(struct hisi_qm *qm);
106 bool hpre_check_alg_support(struct hisi_qm *qm, u32 alg);
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| D | hpre_crypto.c | 228 pci_err(qp->qm->pdev, "Can not start qp!\n"); in hpre_get_qp_and_start()
388 ctx->dev = &qp->qm->pdev->dev; in hpre_ctx_set()
390 hpre = container_of(ctx->qp->qm, struct hpre, qm); in hpre_ctx_set()
2100 static int hpre_register_rsa(struct hisi_qm *qm) in hpre_register_rsa() argument
2104 if (!hpre_check_alg_support(qm, HPRE_DRV_RSA_MASK_CAP)) in hpre_register_rsa()
2110 dev_err(&qm->pdev->dev, "failed to register rsa (%d)!\n", ret); in hpre_register_rsa()
2115 static void hpre_unregister_rsa(struct hisi_qm *qm) in hpre_unregister_rsa() argument
2117 if (!hpre_check_alg_support(qm, HPRE_DRV_RSA_MASK_CAP)) in hpre_unregister_rsa()
2123 static int hpre_register_dh(struct hisi_qm *qm) in hpre_register_dh() argument
2127 if (!hpre_check_alg_support(qm, HPRE_DRV_DH_MASK_CAP)) in hpre_register_dh()
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| /kernel/linux/linux-6.6/drivers/crypto/hisilicon/zip/ |
| D | zip_main.c | 368 struct hisi_qm *qm = s->private; in hzip_diff_regs_show() local
370 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs, in hzip_diff_regs_show()
461 bool hisi_zip_alg_support(struct hisi_qm *qm, u32 alg) in hisi_zip_alg_support() argument
465 cap_val = qm->cap_tables.dev_cap_table[ZIP_DRV_ALG_BITMAP_IDX].cap_val; in hisi_zip_alg_support()
472 static int hisi_zip_set_high_perf(struct hisi_qm *qm) in hisi_zip_set_high_perf() argument
477 val = readl_relaxed(qm->io_base + HZIP_HIGH_PERF_OFFSET); in hisi_zip_set_high_perf()
484 writel(val, qm->io_base + HZIP_HIGH_PERF_OFFSET); in hisi_zip_set_high_perf()
485 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_HIGH_PERF_OFFSET, in hisi_zip_set_high_perf()
489 pci_err(qm->pdev, "failed to set perf mode\n"); in hisi_zip_set_high_perf()
494 static void hisi_zip_open_sva_prefetch(struct hisi_qm *qm) in hisi_zip_open_sva_prefetch() argument
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| D | zip_crypto.c | 231 dev_dbg(&qp_ctx->qp->qm->pdev->dev, "req cache is full!\n"); in hisi_zip_create_req()
340 struct device *dev = &qp->qm->pdev->dev; in hisi_zip_do_work()
412 struct device *dev = &qp->qm->pdev->dev; in hisi_zip_acomp_cb()
448 struct device *dev = &qp_ctx->qp->qm->pdev->dev; in hisi_zip_acompress()
478 struct device *dev = &qp_ctx->qp->qm->pdev->dev; in hisi_zip_adecompress()
506 struct device *dev = &qp->qm->pdev->dev; in hisi_zip_start_qp()
569 hisi_zip = container_of(qps[0]->qm, struct hisi_zip, qm); in hisi_zip_ctx_init()
587 if (hisi_zip->qm.ver < QM_HW_V3) in hisi_zip_ctx_init()
664 dev = &tmp->qp->qm->pdev->dev; in hisi_zip_create_sgl_pool()
677 hisi_acc_free_sgl_pool(&ctx->qp_ctx[HZIP_QPC_COMP].qp->qm->pdev->dev, in hisi_zip_create_sgl_pool()
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| D | zip.h | 27 struct hisi_qm qm; member
85 int hisi_zip_register_to_crypto(struct hisi_qm *qm);
86 void hisi_zip_unregister_from_crypto(struct hisi_qm *qm);
87 bool hisi_zip_alg_support(struct hisi_qm *qm, u32 alg);
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| /kernel/linux/linux-5.10/drivers/crypto/hisilicon/hpre/ |
| D | hpre_main.c | 71 #define HPRE_ADDR(qm, offset) ((qm)->io_base + (offset)) argument
217 static int hpre_cfg_by_dsm(struct hisi_qm *qm) in hpre_cfg_by_dsm() argument
219 struct device *dev = &qm->pdev->dev; in hpre_cfg_by_dsm()
246 static void disable_flr_of_bme(struct hisi_qm *qm) in disable_flr_of_bme() argument
250 val = readl(HPRE_ADDR(qm, QM_PEH_AXUSER_CFG)); in disable_flr_of_bme()
253 writel(val, HPRE_ADDR(qm, QM_PEH_AXUSER_CFG)); in disable_flr_of_bme()
254 writel(PEH_AXUSER_CFG_ENABLE, HPRE_ADDR(qm, QM_PEH_AXUSER_CFG_ENABLE)); in disable_flr_of_bme()
257 static int hpre_set_user_domain_and_cache(struct hisi_qm *qm) in hpre_set_user_domain_and_cache() argument
259 struct device *dev = &qm->pdev->dev; in hpre_set_user_domain_and_cache()
264 writel(HPRE_QM_USR_CFG_MASK, HPRE_ADDR(qm, QM_ARUSER_M_CFG_ENABLE)); in hpre_set_user_domain_and_cache()
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| /kernel/linux/linux-5.10/drivers/crypto/hisilicon/zip/ |
| D | zip_main.c | 252 static int hisi_zip_set_user_domain_and_cache(struct hisi_qm *qm) in hisi_zip_set_user_domain_and_cache() argument
254 void __iomem *base = qm->io_base; in hisi_zip_set_user_domain_and_cache()
256 /* qm user domain */ in hisi_zip_set_user_domain_and_cache()
263 /* qm cache */ in hisi_zip_set_user_domain_and_cache()
282 if (qm->use_sva) { in hisi_zip_set_user_domain_and_cache()
302 static void hisi_zip_hw_error_enable(struct hisi_qm *qm) in hisi_zip_hw_error_enable() argument
306 if (qm->ver == QM_HW_V1) { in hisi_zip_hw_error_enable()
308 qm->io_base + HZIP_CORE_INT_MASK_REG); in hisi_zip_hw_error_enable()
309 dev_info(&qm->pdev->dev, "Does not support hw error handle\n"); in hisi_zip_hw_error_enable()
314 writel(HZIP_CORE_INT_MASK_ALL, qm->io_base + HZIP_CORE_INT_SOURCE); in hisi_zip_hw_error_enable()
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| /kernel/linux/linux-6.6/include/linux/ |
| D | hisi_acc_qm.h | 16 /* qm user domain */
72 /* qm cache */
253 int (*hw_init)(struct hisi_qm *qm);
254 void (*hw_err_enable)(struct hisi_qm *qm);
255 void (*hw_err_disable)(struct hisi_qm *qm);
256 u32 (*get_dev_hw_err_status)(struct hisi_qm *qm);
257 void (*clear_dev_hw_err_status)(struct hisi_qm *qm, u32 err_sts);
258 void (*open_axi_master_ooo)(struct hisi_qm *qm);
259 void (*close_axi_master_ooo)(struct hisi_qm *qm);
260 void (*open_sva_prefetch)(struct hisi_qm *qm);
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| /kernel/linux/linux-6.6/drivers/vfio/pci/hisilicon/ |
| D | hisi_acc_vfio_pci.c | 20 static int qm_wait_dev_not_ready(struct hisi_qm *qm) in qm_wait_dev_not_ready() argument
24 return readl_relaxed_poll_timeout(qm->io_base + QM_VF_STATE, in qm_wait_dev_not_ready()
33 static u32 qm_check_reg_state(struct hisi_qm *qm, u32 regs) in qm_check_reg_state() argument
38 state = readl(qm->io_base + regs); in qm_check_reg_state()
41 state = readl(qm->io_base + regs); in qm_check_reg_state()
48 static int qm_read_regs(struct hisi_qm *qm, u32 reg_addr, in qm_read_regs() argument
57 data[i] = readl(qm->io_base + reg_addr); in qm_read_regs()
64 static int qm_write_regs(struct hisi_qm *qm, u32 reg, in qm_write_regs() argument
73 writel(data[i], qm->io_base + reg + i * QM_REG_ADDR_OFFSET); in qm_write_regs()
78 static int qm_get_vft(struct hisi_qm *qm, u32 *base) in qm_get_vft() argument
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| D | hisi_acc_vfio_pci.h | 63 /* QM match information */
70 /* QM reserved match information */
75 /* QM RW regs */
89 /* QM reserved 5 regs */
92 /* QM memory init information */
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| /kernel/linux/linux-6.6/Documentation/ABI/testing/ |
| D | debugfs-hisi-zip | 26 has a QM. Select the QM which below qm refers to.
39 What: /sys/kernel/debug/hisi_zip/<bdf>/qm/regs
42 Description: Dump of QM related debug registers.
46 What: /sys/kernel/debug/hisi_zip/<bdf>/qm/current_q
49 Description: One QM may contain multiple queues. Select specific queue to
53 What: /sys/kernel/debug/hisi_zip/<bdf>/qm/clear_enable
56 Description: QM debug registers(regs) read clear control. 1 means enable
62 What: /sys/kernel/debug/hisi_zip/<bdf>/qm/err_irq
66 QM task completion.
69 What: /sys/kernel/debug/hisi_zip/<bdf>/qm/aeq_irq
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| D | debugfs-hisi-sec | 13 has a QM. This file can be used to select the QM which below
14 qm refers to.
27 What: /sys/kernel/debug/hisi_sec2/<bdf>/qm/qm_regs
30 Description: Dump of QM related debug registers.
34 What: /sys/kernel/debug/hisi_sec2/<bdf>/qm/current_q
37 Description: One QM of SEC may contain multiple queues. Select specific
41 What: /sys/kernel/debug/hisi_sec2/<bdf>/qm/clear_enable
45 the SEC's QM debug registers.
49 What: /sys/kernel/debug/hisi_sec2/<bdf>/qm/err_irq
53 QM task completion.
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| D | debugfs-hisi-hpre | 27 has a QM. Select the QM which below qm refers to.
46 What: /sys/kernel/debug/hisi_hpre/<bdf>/qm/regs
49 Description: Dump debug registers from the QM.
53 What: /sys/kernel/debug/hisi_hpre/<bdf>/qm/current_q
56 Description: One QM may contain multiple queues. Select specific queue to
60 What: /sys/kernel/debug/hisi_hpre/<bdf>/qm/clear_enable
63 Description: QM debug registers(regs) read clear control. 1 means enable
69 What: /sys/kernel/debug/hisi_hpre/<bdf>/qm/err_irq
73 QM task completion.
76 What: /sys/kernel/debug/hisi_hpre/<bdf>/qm/aeq_irq
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| /kernel/linux/linux-5.10/Documentation/ABI/testing/ |
| D | debugfs-hisi-sec | 13 has a QM. This file can be used to select the QM which below
14 qm refers to.
17 What: /sys/kernel/debug/hisi_sec2/<bdf>/qm/qm_regs
20 Description: Dump of QM related debug registers.
24 What: /sys/kernel/debug/hisi_sec2/<bdf>/qm/current_q
27 Description: One QM of SEC may contain multiple queues. Select specific
31 What: /sys/kernel/debug/hisi_sec2/<bdf>/qm/clear_enable
35 the SEC's QM debug registers.
39 What: /sys/kernel/debug/hisi_sec2/<bdf>/qm/err_irq
43 QM task completion.
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| D | debugfs-hisi-zip | 26 has a QM. Select the QM which below qm refers to.
29 What: /sys/kernel/debug/hisi_zip/<bdf>/qm/regs
32 Description: Dump of QM related debug registers.
36 What: /sys/kernel/debug/hisi_zip/<bdf>/qm/current_q
39 Description: One QM may contain multiple queues. Select specific queue to
43 What: /sys/kernel/debug/hisi_zip/<bdf>/qm/clear_enable
46 Description: QM debug registers(regs) read clear control. 1 means enable
52 What: /sys/kernel/debug/hisi_zip/<bdf>/qm/err_irq
56 QM task completion.
59 What: /sys/kernel/debug/hisi_zip/<bdf>/qm/aeq_irq
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| D | debugfs-hisi-hpre | 27 has a QM. Select the QM which below qm refers to.
36 What: /sys/kernel/debug/hisi_hpre/<bdf>/qm/regs
39 Description: Dump debug registers from the QM.
43 What: /sys/kernel/debug/hisi_hpre/<bdf>/qm/current_q
46 Description: One QM may contain multiple queues. Select specific queue to
50 What: /sys/kernel/debug/hisi_hpre/<bdf>/qm/clear_enable
53 Description: QM debug registers(regs) read clear control. 1 means enable
59 What: /sys/kernel/debug/hisi_hpre/<bdf>/qm/err_irq
63 QM task completion.
66 What: /sys/kernel/debug/hisi_hpre/<bdf>/qm/aeq_irq
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