| /kernel/linux/linux-5.10/drivers/spi/ |
| D | spi-bcm-qspi.c | 25 #include "spi-bcm-qspi.h"
234 static inline bool has_bspi(struct bcm_qspi *qspi) in has_bspi() argument
236 return qspi->bspi_mode; in has_bspi()
240 static inline bool bcm_qspi_has_fastbr(struct bcm_qspi *qspi) in bcm_qspi_has_fastbr() argument
242 if (!has_bspi(qspi) && in bcm_qspi_has_fastbr()
243 ((qspi->mspi_maj_rev >= 1) && in bcm_qspi_has_fastbr()
244 (qspi->mspi_min_rev >= 5))) in bcm_qspi_has_fastbr()
251 static inline bool bcm_qspi_has_sysclk_108(struct bcm_qspi *qspi) in bcm_qspi_has_sysclk_108() argument
253 if (!has_bspi(qspi) && (qspi->mspi_spcr3_sysclk || in bcm_qspi_has_sysclk_108()
254 ((qspi->mspi_maj_rev >= 1) && in bcm_qspi_has_sysclk_108()
[all …]
|
| D | spi-stm32-qspi.c | 94 struct stm32_qspi *qspi; member
128 struct stm32_qspi *qspi = (struct stm32_qspi *)dev_id; in stm32_qspi_irq() local
131 sr = readl_relaxed(qspi->io_base + QSPI_SR); in stm32_qspi_irq()
135 cr = readl_relaxed(qspi->io_base + QSPI_CR); in stm32_qspi_irq()
137 writel_relaxed(cr, qspi->io_base + QSPI_CR); in stm32_qspi_irq()
138 complete(&qspi->data_completion); in stm32_qspi_irq()
154 static int stm32_qspi_tx_poll(struct stm32_qspi *qspi, in stm32_qspi_tx_poll() argument
172 ret = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, in stm32_qspi_tx_poll()
176 dev_err(qspi->dev, "fifo timeout (len:%d stat:%#x)\n", in stm32_qspi_tx_poll()
180 tx_fifo(buf++, qspi->io_base + QSPI_DR); in stm32_qspi_tx_poll()
[all …]
|
| D | spi-ti-qspi.c | 3 * TI QSPI driver
128 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi, in ti_qspi_read() argument
131 return readl(qspi->base + reg); in ti_qspi_read()
134 static inline void ti_qspi_write(struct ti_qspi *qspi, in ti_qspi_write() argument
137 writel(val, qspi->base + reg); in ti_qspi_write()
142 struct ti_qspi *qspi = spi_master_get_devdata(spi->master); in ti_qspi_setup() local
143 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg; in ti_qspi_setup()
148 dev_dbg(qspi->dev, "master busy doing other transfers\n"); in ti_qspi_setup()
152 if (!qspi->spi_max_frequency) { in ti_qspi_setup()
153 dev_err(qspi->dev, "spi max frequency not defined\n"); in ti_qspi_setup()
[all …]
|
| D | spi-zynq-qspi.c | 41 * QSPI Configuration Register bit Masks
44 * of the QSPI controller
57 * QSPI Configuration Register - Baud rate and slave select
67 * QSPI Interrupt Registers bit Masks
72 #define ZYNQ_QSPI_IXR_RX_OVERFLOW_MASK BIT(0) /* QSPI RX FIFO Overflow */
73 #define ZYNQ_QSPI_IXR_TXNFULL_MASK BIT(2) /* QSPI TX FIFO Overflow */
74 #define ZYNQ_QSPI_IXR_TXFULL_MASK BIT(3) /* QSPI TX FIFO is full */
75 #define ZYNQ_QSPI_IXR_RXNEMTY_MASK BIT(4) /* QSPI RX FIFO Not Empty */
76 #define ZYNQ_QSPI_IXR_RXF_FULL_MASK BIT(5) /* QSPI RX FIFO is full */
77 #define ZYNQ_QSPI_IXR_TXF_UNDRFLOW_MASK BIT(6) /* QSPI TX FIFO Underflow */
[all …]
|
| D | spi-zynqmp-gqspi.c | 3 * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
26 /* Generic QSPI register offsets */
141 * struct zynqmp_qspi - Defines qspi driver instance
142 * @regs: Virtual address of the QSPI controller registers
156 * @mode: Defines the mode in which QSPI is operating
254 * The default settings of the QSPI controller's configurable parameters on
266 * - Enable the QSPI controller
354 * @qspi: Pointer to the spi_device structure
357 static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high) in zynqmp_qspi_chipselect() argument
359 struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master); in zynqmp_qspi_chipselect()
[all …]
|
| /kernel/linux/linux-6.6/drivers/spi/ |
| D | spi-bcm-qspi.c | 25 #include "spi-bcm-qspi.h"
255 static inline bool has_bspi(struct bcm_qspi *qspi) in has_bspi() argument
257 return qspi->bspi_mode; in has_bspi()
261 static inline bool bcm_qspi_has_fastbr(struct bcm_qspi *qspi) in bcm_qspi_has_fastbr() argument
263 if (!has_bspi(qspi) && in bcm_qspi_has_fastbr()
264 ((qspi->mspi_maj_rev >= 1) && in bcm_qspi_has_fastbr()
265 (qspi->mspi_min_rev >= 5))) in bcm_qspi_has_fastbr()
272 static inline bool bcm_qspi_has_sysclk_108(struct bcm_qspi *qspi) in bcm_qspi_has_sysclk_108() argument
274 if (!has_bspi(qspi) && (qspi->mspi_spcr3_sysclk || in bcm_qspi_has_sysclk_108()
275 ((qspi->mspi_maj_rev >= 1) && in bcm_qspi_has_sysclk_108()
[all …]
|
| D | spi-ti-qspi.c | 3 * TI QSPI driver
126 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi, in ti_qspi_read() argument
129 return readl(qspi->base + reg); in ti_qspi_read()
132 static inline void ti_qspi_write(struct ti_qspi *qspi, in ti_qspi_write() argument
135 writel(val, qspi->base + reg); in ti_qspi_write()
140 struct ti_qspi *qspi = spi_master_get_devdata(spi->master); in ti_qspi_setup() local
144 dev_dbg(qspi->dev, "master busy doing other transfers\n"); in ti_qspi_setup()
148 if (!qspi->master->max_speed_hz) { in ti_qspi_setup()
149 dev_err(qspi->dev, "spi max frequency not defined\n"); in ti_qspi_setup()
153 spi->max_speed_hz = min(spi->max_speed_hz, qspi->master->max_speed_hz); in ti_qspi_setup()
[all …]
|
| D | spi-stm32-qspi.c | 131 struct stm32_qspi *qspi = (struct stm32_qspi *)dev_id; in stm32_qspi_irq() local
134 cr = readl_relaxed(qspi->io_base + QSPI_CR); in stm32_qspi_irq()
135 sr = readl_relaxed(qspi->io_base + QSPI_SR); in stm32_qspi_irq()
140 writel_relaxed(cr, qspi->io_base + QSPI_CR); in stm32_qspi_irq()
141 complete(&qspi->match_completion); in stm32_qspi_irq()
149 writel_relaxed(cr, qspi->io_base + QSPI_CR); in stm32_qspi_irq()
150 complete(&qspi->data_completion); in stm32_qspi_irq()
166 static int stm32_qspi_tx_poll(struct stm32_qspi *qspi, in stm32_qspi_tx_poll() argument
184 ret = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, in stm32_qspi_tx_poll()
188 dev_err(qspi->dev, "fifo timeout (len:%d stat:%#x)\n", in stm32_qspi_tx_poll()
[all …]
|
| D | spi-microchip-core-qspi.c | 3 * Microchip coreQSPI QSPI controller driver
25 * QSPI Control register mask defines
43 * QSPI Frames register mask defines
55 * QSPI Interrupt Enable register mask defines
65 * QSPI Status register mask defines
84 /* QSPI ready time out value */
88 * QSPI Register offsets.
103 * struct mchp_coreqspi - Defines qspi driver instance
104 * @regs: Virtual address of the QSPI controller registers
105 * @clk: QSPI Operating clock
[all …]
|
| D | spi-zynq-qspi.c | 41 * QSPI Configuration Register bit Masks
44 * of the QSPI controller
57 * QSPI Configuration Register - Baud rate and slave select
67 * QSPI Interrupt Registers bit Masks
72 #define ZYNQ_QSPI_IXR_RX_OVERFLOW_MASK BIT(0) /* QSPI RX FIFO Overflow */
73 #define ZYNQ_QSPI_IXR_TXNFULL_MASK BIT(2) /* QSPI TX FIFO Overflow */
74 #define ZYNQ_QSPI_IXR_TXFULL_MASK BIT(3) /* QSPI TX FIFO is full */
75 #define ZYNQ_QSPI_IXR_RXNEMTY_MASK BIT(4) /* QSPI RX FIFO Not Empty */
76 #define ZYNQ_QSPI_IXR_RXF_FULL_MASK BIT(5) /* QSPI RX FIFO is full */
77 #define ZYNQ_QSPI_IXR_TXF_UNDRFLOW_MASK BIT(6) /* QSPI TX FIFO Underflow */
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/ |
| D | ti_qspi.txt | 1 TI QSPI controller.
4 - compatible : should be "ti,dra7xxx-qspi" or "ti,am4372-qspi".
5 - reg: Should contain QSPI registers location and length.
7 - qspi_base: Qspi configuration register Address space
10 - interrupts: should contain the qspi interrupt number.
12 - ti,hwmods: Name of the hwmod associated to the QSPI
19 - syscon-chipselects: Handle to system control region contains QSPI
22 NOTE: TI QSPI controller requires different pinmux and IODelay
26 specified in the slave nodes of TI QSPI controller without appropriate
32 qspi: qspi@47900000 {
[all …]
|
| D | brcm,spi-bcm-qspi.txt | 26 "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi" : MSPI+BSPI on BRCMSTB SoCs
27 "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi" : Second Instance of MSPI
29 "brcm,spi-bcm7425-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
31 "brcm,spi-bcm7429-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
33 "brcm,spi-bcm7435-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
35 "brcm,spi-bcm7445-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
37 "brcm,spi-bcm7216-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
39 "brcm,spi-bcm7278-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
41 "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi" : MSPI+BSPI on Cygnus, NSP
42 "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi" : NS2 SoCs
[all …]
|
| D | renesas,rspi.yaml | 7 title: Renesas (Quad) Serial Peripheral Interface (RSPI/QSPI)
28 - renesas,qspi-r8a7742 # RZ/G1H
29 - renesas,qspi-r8a7743 # RZ/G1M
30 - renesas,qspi-r8a7744 # RZ/G1N
31 - renesas,qspi-r8a7745 # RZ/G1E
32 - renesas,qspi-r8a77470 # RZ/G1C
33 - renesas,qspi-r8a7790 # R-Car H2
34 - renesas,qspi-r8a7791 # R-Car M2-W
35 - renesas,qspi-r8a7792 # R-Car V2H
36 - renesas,qspi-r8a7793 # R-Car M2-N
[all …]
|
| D | qcom,spi-qcom-qspi.yaml | 5 $id: "http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#"
8 title: Qualcomm Quad Serial Peripheral Interface (QSPI)
14 description: The QSPI controller allows SPI protocol communication in single,
24 - const: qcom,sdm845-qspi
25 - const: qcom,qspi-v1
41 - description: QSPI core clock
50 - const: qspi-config
51 - const: qspi-memory
71 qspi: spi@88df000 {
72 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
|
| D | spi-fsl-qspi.txt | 4 - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi",
5 "fsl,imx7d-qspi", "fsl,imx6ul-qspi",
6 "fsl,ls1021a-qspi", "fsl,ls2080a-qspi"
8 "fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi"
14 - clock-names : Should contain the name of the clocks: "qspi_en" and "qspi".
27 compatible = "fsl,vf610-qspi";
33 clock-names = "qspi_en", "qspi";
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/spi/ |
| D | ti_qspi.txt | 1 TI QSPI controller.
4 - compatible : should be "ti,dra7xxx-qspi" or "ti,am4372-qspi".
5 - reg: Should contain QSPI registers location and length.
7 - qspi_base: Qspi configuration register Address space
10 - interrupts: should contain the qspi interrupt number.
12 - ti,hwmods: Name of the hwmod associated to the QSPI
19 - syscon-chipselects: Handle to system control region contains QSPI
22 NOTE: TI QSPI controller requires different pinmux and IODelay
26 specified in the slave nodes of TI QSPI controller without appropriate
32 qspi: qspi@47900000 {
[all …]
|
| D | cdns,qspi-nor.yaml | 4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
26 const: starfive,jh7110-qspi
37 enum: [ qspi, qspi-ocp, rstc_ref ]
48 enum: [ qspi, qspi-ocp ]
53 const: amd,pensando-elba-qspi
70 - amd,pensando-elba-qspi
71 - ti,k2g-qspi
73 - intel,lgm-qspi
75 - intel,socfpga-qspi
76 - starfive,jh7110-qspi
[all …]
|
| D | fsl,spi-fsl-qspi.yaml | 4 $id: http://devicetree.org/schemas/spi/fsl,spi-fsl-qspi.yaml#
19 - fsl,vf610-qspi
20 - fsl,imx6sx-qspi
21 - fsl,imx7d-qspi
22 - fsl,imx6ul-qspi
23 - fsl,ls1021a-qspi
24 - fsl,ls2080a-qspi
27 - fsl,ls1043a-qspi
28 - const: fsl,ls1021a-qspi
31 - fsl,imx8mq-qspi
[all …]
|
| D | qcom,spi-qcom-qspi.yaml | 4 $id: http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#
7 title: Qualcomm Quad Serial Peripheral Interface (QSPI)
12 description: The QSPI controller allows SPI protocol communication in single,
23 - qcom,sc7180-qspi
24 - qcom,sc7280-qspi
25 - qcom,sdm845-qspi
27 - const: qcom,qspi-v1
46 - description: QSPI core clock
55 - const: qspi-config
56 - const: qspi-memory
[all …]
|
| D | renesas,rspi.yaml | 7 title: Renesas (Quad) Serial Peripheral Interface (RSPI/QSPI)
31 - renesas,qspi-r8a7742 # RZ/G1H
32 - renesas,qspi-r8a7743 # RZ/G1M
33 - renesas,qspi-r8a7744 # RZ/G1N
34 - renesas,qspi-r8a7745 # RZ/G1E
35 - renesas,qspi-r8a77470 # RZ/G1C
36 - renesas,qspi-r8a7790 # R-Car H2
37 - renesas,qspi-r8a7791 # R-Car M2-W
38 - renesas,qspi-r8a7792 # R-Car V2H
39 - renesas,qspi-r8a7793 # R-Car M2-N
[all …]
|
| D | brcm,spi-bcm-qspi.yaml | 4 $id: http://devicetree.org/schemas/spi/brcm,spi-bcm-qspi.yaml#
36 - brcm,spi-bcm7425-qspi
37 - brcm,spi-bcm7429-qspi
38 - brcm,spi-bcm7435-qspi
39 - brcm,spi-bcm7445-qspi
40 - brcm,spi-bcm7216-qspi
41 - brcm,spi-bcm7278-qspi
42 - const: brcm,spi-bcm-qspi
47 - brcm,spi-brcmstb-qspi
49 - brcm,spi-nsp-qspi
[all …]
|
| D | nvidia,tegra210-quad.yaml | 19 - nvidia,tegra210-qspi
20 - nvidia,tegra186-qspi
21 - nvidia,tegra194-qspi
22 - nvidia,tegra234-qspi
23 - nvidia,tegra241-qspi
33 - const: qspi
77 compatible = "nvidia,tegra210-qspi";
84 clock-names = "qspi", "qspi_out";
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/ |
| D | cadence-quadspi.txt | 5 Generic default - "cdns,qspi-nor".
6 For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
7 For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor".
11 address and length of the QSPI Controller data area.
20 - cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch
21 the read data rather than the QSPI clock. Make sure that QSPI return
40 - reset-names : Must include either "qspi" and/or "qspi-ocp".
44 qspi: spi@ff705000 {
45 compatible = "cdns,qspi-nor";
57 reset-names = "qspi", "qspi-ocp";
|
| /kernel/linux/linux-5.10/arch/m68k/include/asm/ |
| D | mcfqspi.h | 3 * Definitions for Freescale Coldfire QSPI module
12 * struct mcfqspi_cs_control - chip select control for the coldfire qspi driver
18 * The QSPI module has 4 hardware chip selects. We don't use them. Instead
20 * platform data for each QSPI master controller. Only the select and
31 * struct mcfqspi_platform_data - platform data for the coldfire qspi driver
32 * @bus_num: board specific identifier for this qspi driver.
33 * @num_chipselects: number of chip selects supported by this qspi driver.
|
| /kernel/linux/linux-6.6/arch/m68k/include/asm/ |
| D | mcfqspi.h | 3 * Definitions for Freescale Coldfire QSPI module
12 * struct mcfqspi_cs_control - chip select control for the coldfire qspi driver
18 * The QSPI module has 4 hardware chip selects. We don't use them. Instead
20 * platform data for each QSPI master controller. Only the select and
31 * struct mcfqspi_platform_data - platform data for the coldfire qspi driver
32 * @bus_num: board specific identifier for this qspi driver.
33 * @num_chipselects: number of chip selects supported by this qspi driver.
|