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/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/
Dmemory.json8 …ECC or parity) in protected CPUs RAMs. On the core, this event counts errors in the caches (includ…
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/
Dmemory.json8 …ECC or parity) in protected CPUs RAMs. On the core, this event counts errors in the caches (includ…
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/arm64/ampere/emag/
Dmemory.json21 …t counts any correctable or uncorrectable memory error (ECC or parity) in the protected core RAMs",
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/arm64/ampere/emag/
Dmemory.json24 …t counts any correctable or uncorrectable memory error (ECC or parity) in the protected core RAMs",
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/
Dexception.json6 …t counts any correctable or uncorrectable memory error (ECC or parity) in the protected core RAMs",
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/
Dexception.json8 …t counts any correctable or uncorrectable memory error (ECC or parity) in the protected core RAMs",
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/soc/ti/
Dti,pruss.yaml19 instruction RAMs, some internal peripheral modules to facilitate industrial
35 acts on a primary Data RAM (there are usually 2 Data RAMs) at its address
92 The various Data RAMs within a single PRU-ICSS unit are represented as a
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/ti/
Dti,pruss.yaml19 instruction RAMs, some internal peripheral modules to facilitate industrial
35 acts on a primary Data RAM (there are usually 2 Data RAMs) at its address
99 The various Data RAMs within a single PRU-ICSS unit are represented as a
/kernel/linux/linux-6.6/arch/xtensa/variants/fsf/include/variant/
Dcore.h165 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
167 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
168 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/kernel/linux/linux-5.10/arch/xtensa/variants/fsf/include/variant/
Dcore.h165 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
167 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
168 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/kernel/linux/linux-6.6/arch/arc/
DKconfig244 Single Cycle RAMS to store Fast Path Code
254 Single Cycle RAMS to store Fast Path Data
/kernel/linux/linux-5.10/arch/arc/
DKconfig261 Single Cycle RAMS to store Fast Path Code
271 Single Cycle RAMS to store Fast Path Data
/kernel/linux/linux-5.10/arch/xtensa/variants/dc232b/include/variant/
Dcore.h172 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
174 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
175 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/kernel/linux/linux-6.6/arch/xtensa/variants/test_mmuhifi_c3/include/variant/
Dcore.h185 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
187 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
188 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/kernel/linux/linux-5.10/arch/xtensa/variants/test_mmuhifi_c3/include/variant/
Dcore.h185 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
187 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
188 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/kernel/linux/linux-6.6/arch/xtensa/variants/dc232b/include/variant/
Dcore.h172 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
174 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
175 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/kernel/linux/linux-5.10/arch/powerpc/platforms/8xx/
DKconfig154 This microcode relocates SMC1 and SMC2 parameter RAMs at
/kernel/linux/linux-6.6/drivers/misc/eeprom/
DKconfig5 tristate "I2C EEPROMs / RAMs / ROMs from most vendors"
/kernel/linux/linux-6.6/arch/powerpc/platforms/8xx/
DKconfig155 This microcode relocates SMC1 and SMC2 parameter RAMs at
/kernel/linux/linux-5.10/drivers/misc/eeprom/
DKconfig5 tristate "I2C EEPROMs / RAMs / ROMs from most vendors"
/kernel/linux/linux-6.6/arch/xtensa/variants/dc233c/include/variant/
Dcore.h218 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
220 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
221 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/kernel/linux/linux-5.10/arch/xtensa/variants/dc233c/include/variant/
Dcore.h218 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
220 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
221 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/kernel/linux/linux-6.6/drivers/remoteproc/
Dkeystone_remoteproc.c242 * Custom function to translate a DSP device address (internal RAMs only) to a
243 * kernel virtual address. The DSPs can access their RAMs at either an internal
/kernel/linux/linux-5.10/drivers/remoteproc/
Dkeystone_remoteproc.c242 * Custom function to translate a DSP device address (internal RAMs only) to a
243 * kernel virtual address. The DSPs can access their RAMs at either an internal
Dti_k3_dsp_remoteproc.c224 * internal RAMs. The .prepare() ops is invoked by remoteproc core before any
350 * Custom function to translate a DSP device address (internal RAMs only) to a
351 * kernel virtual address. The DSPs can access their RAMs at either an internal

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