Searched full:ref_sel (Results 1 – 11 of 11) sorted by relevance
20 rate is specified by REF_SEL pins and a value from the primary23 - refclk-frequency: Frequency of the REFCLK signal as defined by REF_SEL
236 u32 ref_sel; member612 u32 ref_sel; in ad4130_setup_info_eq()623 a->ref_sel != b->ref_sel || in ad4130_setup_info_eq()724 FIELD_PREP(AD4130_CONFIG_REF_SEL_MASK, setup_info->ref_sel) | in ad4130_write_slot_setup()1014 if (val == st->scale_tbls[setup_info->ref_sel][pga][0] && in ad4130_set_channel_pga()1015 val2 == st->scale_tbls[setup_info->ref_sel][pga][1]) in ad4130_set_channel_pga()1134 *val = st->scale_tbls[setup_info->ref_sel][setup_info->pga][0]; in ad4130_read_raw()1135 *val2 = st->scale_tbls[setup_info->ref_sel][setup_info->pga][1]; in ad4130_read_raw()1167 *vals = (int *)st->scale_tbls[setup_info->ref_sel]; in ad4130_read_avail()1168 *length = ARRAY_SIZE(st->scale_tbls[setup_info->ref_sel]) * 2; in ad4130_read_avail()[all …]
65 that clock signal is always available, its rate is specified by REF_SEL75 Frequency of the REFCLK signal as defined by REF_SEL pins. If not
144 u8 ref_sel; member
271 ts->stmpe->ref_sel = val; in stmpe_ts_get_platform_info()
52 PDEBUG("reg0 CFG1 ref_sel %d hibernate %d rf_vco_reg_en %d"
269 ts->stmpe->ref_sel = val; in stmpe_ts_get_platform_info()
552 STMPE_REF_SEL(stmpe->ref_sel); in stmpe811_adc_common_init()1396 stmpe->ref_sel = val; in stmpe_probe()
554 STMPE_REF_SEL(stmpe->ref_sel); in stmpe811_adc_common_init()1407 stmpe->ref_sel = val; in stmpe_probe()