| /kernel/linux/linux-6.6/drivers/media/pci/bt8xx/ |
| D | btcx-risc.c | 4 btcx-risc.c
6 bt848/bt878/cx2388x risc code generator.
23 #include "btcx-risc.h"
37 /* allocate/free risc memory */
42 struct btcx_riscmem *risc) in btcx_riscmem_free() argument
44 if (NULL == risc->cpu) in btcx_riscmem_free()
49 memcnt, (unsigned long)risc->dma); in btcx_riscmem_free()
51 dma_free_coherent(&pci->dev, risc->size, risc->cpu, risc->dma); in btcx_riscmem_free()
52 memset(risc,0,sizeof(*risc)); in btcx_riscmem_free()
56 struct btcx_riscmem *risc, in btcx_riscmem_alloc() argument
[all …]
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| D | bttv-risc.c | 4 bttv-risc.c -- interfaces to other kernel modules
6 bttv risc code handling
32 /* risc code generators */
35 bttv_risc_packed(struct bttv *btv, struct btcx_riscmem *risc, in bttv_risc_packed() argument
46 /* estimate risc mem: worst case is one write per page border + in bttv_risc_packed()
54 if ((rc = btcx_riscmem_alloc(btv->c.pci,risc,instructions)) < 0) in bttv_risc_packed()
58 rp = risc->cpu; in bttv_risc_packed()
108 risc->jmp = rp; in bttv_risc_packed()
109 WARN_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size); in bttv_risc_packed()
114 bttv_risc_planar(struct bttv *btv, struct btcx_riscmem *risc, in bttv_risc_planar() argument
[all …]
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| /kernel/linux/linux-6.6/Documentation/riscv/ |
| D | patch-acceptance.rst | 8 The RISC-V instruction set architecture is developed in the open:
13 challenge for RISC-V Linux maintenance. Linux maintainers disapprove
16 principles to the RISC-V-related code that will be accepted for
22 RISC-V has a patchwork instance, where the status of patches can be checked:
26 If your patch does not appear in the default view, the RISC-V maintainers have
31 RISC-V `for-next` and `fixes` branches, depending on whether the patch has been
32 detected as a fix. Failing those, it will use the RISC-V `master` branch.
42 specifications from the RISC-V foundation this means "Frozen" or
47 Additionally, the RISC-V specification allows implementers to create
49 to go through any review or ratification process by the RISC-V
[all …]
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| D | boot.rst | 4 RISC-V Kernel Boot Requirements and Constraints
10 This document describes what the RISC-V kernel expects from bootloaders and
19 The RISC-V kernel expects the following of bootloaders and platform firmware:
24 The RISC-V kernel expects:
32 The RISC-V kernel expects:
39 The RISC-V kernel must not map any resident memory, or memory protected with
46 The RISC-V kernel expects to be placed at a PMD boundary (2MB aligned for rv64
53 The firmware can pass either a devicetree or ACPI tables to the RISC-V kernel.
71 support older firmwares without SBI HSM extension and M-mode RISC-V kernel.
75 booting the RISC-V kernel because it can support CPU hotplug and kexec.
[all …]
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| D | hwprobe.rst | 3 RISC-V Hardware Probing Interface
6 The RISC-V hardware probing interface is based around a single syscall, which
35 as defined by the RISC-V privileged architecture specification.
38 defined by the RISC-V privileged architecture specification.
41 defined by the RISC-V privileged architecture specification.
62 minimumNumber/maximumNumber, not minNum/maxNum") of the RISC-V ISA manual.
65 by version 2.2 of the RISC-V ISA manual.
68 version 1.0 of the RISC-V Vector extension manual.
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| /kernel/linux/linux-5.10/drivers/media/pci/bt8xx/ |
| D | btcx-risc.c | 4 btcx-risc.c
6 bt848/bt878/cx2388x risc code generator.
23 #include "btcx-risc.h"
37 /* allocate/free risc memory */
42 struct btcx_riscmem *risc) in btcx_riscmem_free() argument
44 if (NULL == risc->cpu) in btcx_riscmem_free()
49 memcnt, (unsigned long)risc->dma); in btcx_riscmem_free()
51 pci_free_consistent(pci, risc->size, risc->cpu, risc->dma); in btcx_riscmem_free()
52 memset(risc,0,sizeof(*risc)); in btcx_riscmem_free()
56 struct btcx_riscmem *risc, in btcx_riscmem_alloc() argument
[all …]
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| D | bttv-risc.c | 4 bttv-risc.c -- interfaces to other kernel modules
6 bttv risc code handling
32 /* risc code generators */
35 bttv_risc_packed(struct bttv *btv, struct btcx_riscmem *risc, in bttv_risc_packed() argument
46 /* estimate risc mem: worst case is one write per page border + in bttv_risc_packed()
54 if ((rc = btcx_riscmem_alloc(btv->c.pci,risc,instructions)) < 0) in bttv_risc_packed()
58 rp = risc->cpu; in bttv_risc_packed()
108 risc->jmp = rp; in bttv_risc_packed()
109 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size); in bttv_risc_packed()
114 bttv_risc_planar(struct bttv *btv, struct btcx_riscmem *risc, in bttv_risc_planar() argument
[all …]
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| /kernel/linux/linux-5.10/drivers/media/pci/cx25821/ |
| D | cx25821-core.c | 299 static int cx25821_risc_decode(u32 risc) in cx25821_risc_decode() argument
331 risc, instr[risc >> 28] ? instr[risc >> 28] : "INVALID"); in cx25821_risc_decode()
333 if (risc & (1 << (i + 12))) in cx25821_risc_decode()
336 pr_cont(" count=%d ]\n", risc & 0xfff); in cx25821_risc_decode()
337 return incr[risc >> 28] ? incr[risc >> 28] : 1; in cx25821_risc_decode()
426 unsigned int bpl, u32 risc) in cx25821_sram_channel_setup() argument
468 cx_write(ch->cmds_start + 0, risc); in cx25821_sram_channel_setup()
494 unsigned int bpl, u32 risc) in cx25821_sram_channel_setup_audio() argument
532 cx_write(ch->cmds_start + 0, risc); in cx25821_sram_channel_setup_audio()
562 "init risc lo", in cx25821_sram_channel_dump()
[all …]
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| /kernel/linux/linux-6.6/drivers/media/pci/cx25821/ |
| D | cx25821-core.c | 299 static int cx25821_risc_decode(u32 risc) in cx25821_risc_decode() argument
331 risc, instr[risc >> 28] ? instr[risc >> 28] : "INVALID"); in cx25821_risc_decode()
333 if (risc & (1 << (i + 12))) in cx25821_risc_decode()
336 pr_cont(" count=%d ]\n", risc & 0xfff); in cx25821_risc_decode()
337 return incr[risc >> 28] ? incr[risc >> 28] : 1; in cx25821_risc_decode()
419 unsigned int bpl, u32 risc) in cx25821_sram_channel_setup() argument
461 cx_write(ch->cmds_start + 0, risc); in cx25821_sram_channel_setup()
487 unsigned int bpl, u32 risc) in cx25821_sram_channel_setup_audio() argument
525 cx_write(ch->cmds_start + 0, risc); in cx25821_sram_channel_setup_audio()
555 "init risc lo", in cx25821_sram_channel_dump()
[all …]
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| /kernel/linux/linux-6.6/drivers/media/pci/cx88/ |
| D | cx88-vbi.c | 59 VBI_LINE_LENGTH, buf->risc.dma); in cx8800_start_vbi_dma()
147 return cx88_risc_buffer(dev->pci, &buf->risc, sgt->sgl, in buffer_prepare()
158 struct cx88_riscmem *risc = &buf->risc; in buffer_finish() local
160 if (risc->cpu) in buffer_finish()
161 dma_free_coherent(&dev->pci->dev, risc->size, risc->cpu, in buffer_finish()
162 risc->dma); in buffer_finish()
163 memset(risc, 0, sizeof(*risc)); in buffer_finish()
175 buf->risc.cpu[1] = cpu_to_le32(buf->risc.dma + 8); in buffer_queue()
176 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_CNT_INC); in buffer_queue()
177 buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma + 8); in buffer_queue()
[all …]
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| D | cx88-core.c | 130 int cx88_risc_buffer(struct pci_dev *pci, struct cx88_riscmem *risc, in cx88_risc_buffer() argument
145 * estimate risc mem: worst case is one write per page border + in cx88_risc_buffer()
153 risc->size = instructions * 8; in cx88_risc_buffer()
154 risc->dma = 0; in cx88_risc_buffer()
155 risc->cpu = dma_alloc_coherent(&pci->dev, risc->size, &risc->dma, in cx88_risc_buffer()
157 if (!risc->cpu) in cx88_risc_buffer()
160 /* write risc instructions */ in cx88_risc_buffer()
161 rp = risc->cpu; in cx88_risc_buffer()
171 risc->jmp = rp; in cx88_risc_buffer()
172 WARN_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size); in cx88_risc_buffer()
[all …]
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| /kernel/linux/linux-5.10/drivers/media/pci/cx88/ |
| D | cx88-vbi.c | 59 VBI_LINE_LENGTH, buf->risc.dma); in cx8800_start_vbi_dma()
147 return cx88_risc_buffer(dev->pci, &buf->risc, sgt->sgl, in buffer_prepare()
158 struct cx88_riscmem *risc = &buf->risc; in buffer_finish() local
160 if (risc->cpu) in buffer_finish()
161 pci_free_consistent(dev->pci, risc->size, risc->cpu, risc->dma); in buffer_finish()
162 memset(risc, 0, sizeof(*risc)); in buffer_finish()
174 buf->risc.cpu[1] = cpu_to_le32(buf->risc.dma + 8); in buffer_queue()
175 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_CNT_INC); in buffer_queue()
176 buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma + 8); in buffer_queue()
184 buf->risc.cpu[0] |= cpu_to_le32(RISC_IRQ1); in buffer_queue()
[all …]
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| D | cx88-core.c | 130 int cx88_risc_buffer(struct pci_dev *pci, struct cx88_riscmem *risc, in cx88_risc_buffer() argument
145 * estimate risc mem: worst case is one write per page border + in cx88_risc_buffer()
153 risc->size = instructions * 8; in cx88_risc_buffer()
154 risc->dma = 0; in cx88_risc_buffer()
155 risc->cpu = pci_zalloc_consistent(pci, risc->size, &risc->dma); in cx88_risc_buffer()
156 if (!risc->cpu) in cx88_risc_buffer()
159 /* write risc instructions */ in cx88_risc_buffer()
160 rp = risc->cpu; in cx88_risc_buffer()
170 risc->jmp = rp; in cx88_risc_buffer()
171 WARN_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size); in cx88_risc_buffer()
[all …]
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| /kernel/linux/linux-5.10/Documentation/riscv/ |
| D | patch-acceptance.rst | 8 The RISC-V instruction set architecture is developed in the open:
13 challenge for RISC-V Linux maintenance. Linux maintainers disapprove
16 principles to the RISC-V-related code that will be accepted for
23 "Frozen" or "Ratified" by the RISC-V Foundation. (Developers may, of
27 Additionally, the RISC-V specification allows implementors to create
29 to go through any review or ratification process by the RISC-V
32 RISC-V extensions, we'll only to accept patches for extensions that
33 have been officially frozen or ratified by the RISC-V Foundation.
|
| /kernel/linux/linux-5.10/drivers/media/pci/tw68/ |
| D | tw68-risc.c | 24 * @rp: pointer to current risc program position
120 * @top_offset: offset within the risc program area for the
122 * @bottom_offset: offset within the risc program area for the
146 * estimate risc mem: worst case is one write per page border + in tw68_risc_buffer()
158 /* write risc instructions */ in tw68_risc_buffer()
170 /* assure risc buffer hasn't overflowed */ in tw68_risc_buffer()
179 static void tw68_risc_decode(u32 risc, u32 addr)
196 p = RISC_OP(risc);
197 if (!(risc & 0x80000000) || !instr[p].name) {
198 pr_debug("0x%08x [ INVALID ]\n", risc);
[all …]
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| /kernel/linux/linux-5.10/drivers/media/pci/cx23885/ |
| D | cx23885-core.c | 38 * encountered is "mpeg risc op code error". Only Ryzen platforms employ
45 MODULE_PARM_DESC(dma_reset_workaround, "periodic RiSC dma engine reset; 0-force disable, 1-driver d…
384 static int cx23885_risc_decode(u32 risc) in cx23885_risc_decode() argument
415 printk(KERN_DEBUG "0x%08x [ %s", risc, in cx23885_risc_decode()
416 instr[risc >> 28] ? instr[risc >> 28] : "INVALID"); in cx23885_risc_decode()
418 if (risc & (1 << (i + 12))) in cx23885_risc_decode()
420 pr_cont(" count=%d ]\n", risc & 0xfff); in cx23885_risc_decode()
421 return incr[risc >> 28] ? incr[risc >> 28] : 1; in cx23885_risc_decode()
456 unsigned int bpl, u32 risc) in cx23885_sram_channel_setup() argument
499 cx_write(ch->cmds_start + 0, risc); in cx23885_sram_channel_setup()
[all …]
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| D | cx23885-vbi.c | 94 VBI_LINE_LENGTH, buf->risc.dma); in cx23885_start_vbi_dma()
107 cx_set(VID_A_DMA_CTL, 0x22); /* FIFO and RISC enable */ in cx23885_start_vbi_dma()
144 cx23885_risc_vbibuffer(dev->pci, &buf->risc, in buffer_prepare()
162 * The risc program for each buffer works as follows: it starts with a simple
167 * This is the risc program of the first buffer to be queued if the active list
192 buf->risc.cpu[1] = cpu_to_le32(buf->risc.dma + 12); in buffer_queue()
193 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_CNT_INC); in buffer_queue()
194 buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma + 12); in buffer_queue()
195 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */ in buffer_queue()
205 buf->risc.cpu[0] |= cpu_to_le32(RISC_IRQ1); in buffer_queue()
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/timer/ |
| D | riscv,timer.yaml | 7 title: RISC-V timer
13 RISC-V platforms always have a RISC-V timer device for the supervisor-mode
14 based on the time CSR defined by the RISC-V privileged specification. The
15 timer interrupts of this device are configured using the RISC-V SBI Time
16 extension or the RISC-V Sstc extension.
18 The clock frequency of RISC-V timer device is specified via the
|
| /kernel/linux/linux-6.6/drivers/media/pci/cx23885/ |
| D | cx23885-core.c | 38 * encountered is "mpeg risc op code error". Only Ryzen platforms employ
45 MODULE_PARM_DESC(dma_reset_workaround, "periodic RiSC dma engine reset; 0-force disable, 1-driver d…
384 static int cx23885_risc_decode(u32 risc) in cx23885_risc_decode() argument
415 printk(KERN_DEBUG "0x%08x [ %s", risc, in cx23885_risc_decode()
416 instr[risc >> 28] ? instr[risc >> 28] : "INVALID"); in cx23885_risc_decode()
418 if (risc & (1 << (i + 12))) in cx23885_risc_decode()
420 pr_cont(" count=%d ]\n", risc & 0xfff); in cx23885_risc_decode()
421 return incr[risc >> 28] ? incr[risc >> 28] : 1; in cx23885_risc_decode()
456 unsigned int bpl, u32 risc) in cx23885_sram_channel_setup() argument
499 cx_write(ch->cmds_start + 0, risc); in cx23885_sram_channel_setup()
[all …]
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| D | cx23885-vbi.c | 94 VBI_LINE_LENGTH, buf->risc.dma); in cx23885_start_vbi_dma()
107 cx_set(VID_A_DMA_CTL, 0x22); /* FIFO and RISC enable */ in cx23885_start_vbi_dma()
144 cx23885_risc_vbibuffer(dev->pci, &buf->risc, in buffer_prepare()
162 * The risc program for each buffer works as follows: it starts with a simple
167 * This is the risc program of the first buffer to be queued if the active list
192 buf->risc.cpu[1] = cpu_to_le32(buf->risc.dma + 12); in buffer_queue()
193 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_CNT_INC); in buffer_queue()
194 buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma + 12); in buffer_queue()
195 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */ in buffer_queue()
205 buf->risc.cpu[0] |= cpu_to_le32(RISC_IRQ1); in buffer_queue()
[all …]
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| /kernel/linux/linux-6.6/drivers/media/pci/tw68/ |
| D | tw68-risc.c | 24 * @rp: pointer to current risc program position
120 * @top_offset: offset within the risc program area for the
122 * @bottom_offset: offset within the risc program area for the
146 * estimate risc mem: worst case is one write per page border + in tw68_risc_buffer()
159 /* write risc instructions */ in tw68_risc_buffer()
171 /* assure risc buffer hasn't overflowed */ in tw68_risc_buffer()
180 static void tw68_risc_decode(u32 risc, u32 addr)
197 p = RISC_OP(risc);
198 if (!(risc & 0x80000000) || !instr[p].name) {
199 pr_debug("0x%08x [ INVALID ]\n", risc);
[all …]
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| /kernel/linux/linux-5.10/Documentation/translations/it_IT/riscv/ |
| D | patch-acceptance.rst | 12 L'insieme di istruzioni RISC-V sono sviluppate in modo aperto: le
18 supporto RISC-V nel kernel Linux. I manutentori Linux non amano
22 relativo all'architettura RISC-V che verrà accettato per l'inclusione
29 RISC-V li classifica come "Frozen" o "Retified". (Ovviamente, gli
33 In aggiunta, la specifica RISC-V permette agli implementatori di
35 attraverso il processo di revisione della fondazione RISC-V. Per
38 state ufficialmente accettate dalla fondazione RISC-V. (Ovviamente,
|
| /kernel/linux/linux-6.6/Documentation/translations/it_IT/riscv/ |
| D | patch-acceptance.rst | 12 L'insieme di istruzioni RISC-V sono sviluppate in modo aperto: le
18 supporto RISC-V nel kernel Linux. I manutentori Linux non amano
22 relativo all'architettura RISC-V che verrà accettato per l'inclusione
29 RISC-V li classifica come "Frozen" o "Retified". (Ovviamente, gli
33 In aggiunta, la specifica RISC-V permette agli implementatori di
35 attraverso il processo di revisione della fondazione RISC-V. Per
38 state ufficialmente accettate dalla fondazione RISC-V. (Ovviamente,
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 7 title: RISC-V bindings for 'cpus' DT nodes
14 This document uses some terminology common to the RISC-V community
18 mandated by the RISC-V ISA: a PC and some registers. This
39 Identifies that the hart uses the RISC-V instruction set
45 hart. These values originate from the RISC-V Privileged
56 Identifies the specific RISC-V instruction set architecture
57 supported by the hart. These are documented in the RISC-V
69 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,cpu-intc.txt | 1 RISC-V Hart-Level Interrupt Controller (HLIC)
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
18 All RISC-V systems that conform to the supervisor ISA specification are
29 RISC-V supervisor ISA manual, with only the following three interrupts being
|