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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/power/reset/
Dkeystone-reset.txt1 * Device tree bindings for Texas Instruments keystone reset
3 This node is intended to allow SoC reset in case of software reset
6 The Keystone SoCs can contain up to 4 watchdog timers to reset
7 SoC. Each watchdog timer event input is connected to the Reset Mux
8 block. The Reset Mux block can be configured to cause reset or not.
10 Additionally soft or hard reset can be configured.
14 - compatible: ti,keystone-reset
16 - ti,syscon-pll: phandle/offset pair. The phandle to syscon used to
18 reset control registers.
20 - ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/power/reset/
Dkeystone-reset.txt1 * Device tree bindings for Texas Instruments keystone reset
3 This node is intended to allow SoC reset in case of software reset
6 The Keystone SoCs can contain up to 4 watchdog timers to reset
7 SoC. Each watchdog timer event input is connected to the Reset Mux
8 block. The Reset Mux block can be configured to cause reset or not.
10 Additionally soft or hard reset can be configured.
14 - compatible: ti,keystone-reset
16 - ti,syscon-pll: phandle/offset pair. The phandle to syscon used to
18 reset control registers.
20 - ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
[all …]
/kernel/linux/linux-6.6/drivers/scsi/snic/
Dsnic.h1 /* SPDX-License-Identifier: GPL-2.0-only */
47 #define SNIC_TAG_DEV_RST BIT(29) /* Tag for device reset */
48 #define SNIC_TAG_IOCTL_DEV_RST BIT(28) /* Tag for User Device Reset */
49 #define SNIC_TAG_MASK (BIT(24) - 1) /* Mask for lookup */
50 #define SNIC_NO_TAG -1
96 (((struct snic_internal_io_state *)scsi_cmd_priv(Cmnd))->rqi)
98 (((struct snic_internal_io_state *)scsi_cmd_priv(Cmnd))->state)
100 (((struct snic_internal_io_state *)scsi_cmd_priv(Cmnd))->abts_status)
102 (((struct snic_internal_io_state *)scsi_cmd_priv(Cmnd))->lr_status)
104 (((struct snic_internal_io_state *)scsi_cmd_priv(Cmnd))->flags)
[all …]
/kernel/linux/linux-6.6/Documentation/ABI/stable/
Dsysfs-driver-mlxreg-io1 What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/asic_health
6 0 - health failed, 2 - health OK, 3 - ASIC in booting state.
10 What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld1_version
11 What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld2_version
20 What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/fan_dir
25 forward direction - relevant bit is set 0;
26 reversed direction - relevant bit is set 1.
30 What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld3_version
39 What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/jtag_enable
48 What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/select_iio
[all …]
/kernel/linux/linux-5.10/drivers/scsi/snic/
Dsnic.h61 #define SNIC_TAG_DEV_RST BIT(29) /* Tag for device reset */
62 #define SNIC_TAG_IOCTL_DEV_RST BIT(28) /* Tag for User Device Reset */
63 #define SNIC_TAG_MASK (BIT(24) - 1) /* Mask for lookup */
64 #define SNIC_NO_TAG -1
110 (((struct snic_internal_io_state *)scsi_cmd_priv(Cmnd))->rqi)
112 (((struct snic_internal_io_state *)scsi_cmd_priv(Cmnd))->state)
114 (((struct snic_internal_io_state *)scsi_cmd_priv(Cmnd))->abts_status)
116 (((struct snic_internal_io_state *)scsi_cmd_priv(Cmnd))->lr_status)
118 (((struct snic_internal_io_state *)scsi_cmd_priv(Cmnd))->flags)
276 /* discovery related */
[all …]
/kernel/linux/linux-6.6/drivers/ntb/hw/idt/
Dntb_hw_idt.h7 * Copyright (C) 2016-2018 T-Platforms JSC All Rights Reserved.
36 * IDT PCIe-switch NTB Linux driver
39 * Serge Semin <fancer.lancer@gmail.com>, <Sergey.Semin@t-platforms.ru>
55 * the supported IDT PCIe-switches
66 * IDT PCIe-switches device IDs
78 * NT-function Configuration Space registers
79 * NOTE 1) The IDT PCIe-switch internal data is little-endian
83 * with byte-enables corresponding to their native size or
86 * So to simplify the driver code, there is only DWORD-sized read/write
107 /* IDT Proprietary NT-port-specific registers */
[all …]
/kernel/linux/linux-5.10/drivers/ntb/hw/idt/
Dntb_hw_idt.h7 * Copyright (C) 2016-2018 T-Platforms JSC All Rights Reserved.
36 * IDT PCIe-switch NTB Linux driver
39 * Serge Semin <fancer.lancer@gmail.com>, <Sergey.Semin@t-platforms.ru>
55 * the supported IDT PCIe-switches
66 * IDT PCIe-switches device IDs
78 * NT-function Configuration Space registers
79 * NOTE 1) The IDT PCIe-switch internal data is little-endian
83 * with byte-enables corresponding to their native size or
86 * So to simplify the driver code, there is only DWORD-sized read/write
107 /* IDT Proprietary NT-port-specific registers */
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/socionext/
Dsocionext,uniphier-sdctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-sdctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
14 attached outside SDHC, and has some SD related functions such as
15 clock control, reset control, mode switch, and so on.
20 - enum:
21 - socionext,uniphier-pro5-sdctrl
22 - socionext,uniphier-pxs2-sdctrl
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dmediatek,mtmips-sysc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mtmips-sysc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
15 and reset related ones so this node is both clock and reset provider
24 - enum:
25 - ralink,mt7620-sysc
26 - ralink,mt7628-sysc
27 - ralink,mt7688-sysc
[all …]
Dallwinner,sun9i-a80-mmc-config-clk.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-mmc-config-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 There is one clock/reset output per mmc controller. The number of
18 related to the overall mmc block.
21 "#clock-cells":
27 "#reset-cells":
[all …]
Dmediatek,mt7621-sysc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt7621-sysc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
21 [1]: <include/dt-bindings/clock/mt7621-clk.h>.
25 This node is also a reset provider for all the peripherals.
27 Reset related bits are defined in:
28 [2]: <include/dt-bindings/reset/mt7621-reset.h>.
33 - const: mediatek,mt7621-sysc
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/power/
Dallwinner,sun20i-d1-ppu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/allwinner,sun20i-d1-ppu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Samuel Holland <samuel@sholland.org>
13 D1 and related SoCs contain a power domain controller for the CPUs, GPU, and
14 video-related hardware.
19 - allwinner,sun20i-d1-ppu
31 '#power-domain-cells':
35 - compatible
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-omap1/
Dreset.c1 // SPDX-License-Identifier: GPL-2.0
3 * OMAP1 reset support
13 /* ARM_SYSST bit shifts related to SoC reset sources */
19 /* Standardized reset source bits (across all OMAP SoCs) */
30 * "Global Software Reset Affects Traffic Controller Frequency". in omap1_restart()
41 * omap1_get_reset_sources - return the source of the SoC's last reset
43 * Returns bits that represent the last reset source for the SoC. The
/kernel/linux/linux-5.10/arch/arm/mach-omap1/
Dreset.c1 // SPDX-License-Identifier: GPL-2.0
3 * OMAP1 reset support
14 /* ARM_SYSST bit shifts related to SoC reset sources */
20 /* Standardized reset source bits (across all OMAP SoCs) */
31 * "Global Software Reset Affects Traffic Controller Frequency". in omap1_restart()
42 * omap1_get_reset_sources - return the source of the SoC's last reset
44 * Returns bits that represent the last reset source for the SoC. The
/kernel/linux/linux-6.6/include/linux/
Dresctrl.h1 /* SPDX-License-Identifier: GPL-2.0 */
22 * enum resctrl_conf_type - The type of configuration.
46 * struct resctrl_staged_config - parsed configuration to be applied
56 * struct rdt_domain - group of CPUs sharing a resctrl resource
67 * @plr: pseudo-locked region (if any) associated with domain
90 * struct resctrl_cache - Cache allocation related data
110 * enum membw_throttle_mode - System's memory bandwidth throttling mode
124 * struct resctrl_membw - Memory bandwidth allocation related data
128 * @arch_needs_linear: True if we can't configure non-linear resources
148 * struct rdt_resource - attributes of a resctrl resource
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dallwinner,sun9i-a80-mmc-config-clk.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-mmc-config-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 There is one clock/reset output per mmc controller. The number of
18 related to the overall mmc block.
21 "#clock-cells":
27 "#reset-cells":
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mfd/
Daspeed-lpc.txt5 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
11 The LPC controller is represented as a multi-function device to account for the
24 APB-to-LPC bridging amonst other functions.
27 as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
39 [1] https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2168.pdf?key=7c888374547021…
40 …el.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev…
46 - compatible: One of:
47 "aspeed,ast2400-lpc", "simple-mfd"
48 "aspeed,ast2500-lpc", "simple-mfd"
50 - reg: contains the physical address and length values of the Aspeed
[all …]
/kernel/linux/linux-6.6/drivers/soc/renesas/
Drcar-rst.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen1 RESET/WDT, R-Car Gen2, Gen3, and RZ/G RST Driver
11 #include <linux/soc/renesas/rcar-rst.h>
38 * Most of the R-Car Gen3 SoCs have an ARM Realtime Core.
47 return -EINVAL; in rcar_rst_set_gen3_rproc_boot_addr()
76 /* V3U firmware doesn't enable WDT reset and there won't be updates anymore */
78 .modemr = 0x00, /* MODEMR0 and it has CPG related bits */
83 .modemr = 0x00, /* MODEMR0 and it has CPG related bits */
87 /* RZ/G1 is handled like R-Car Gen2 */
88 { .compatible = "renesas,r8a7742-rst", .data = &rcar_rst_gen2 },
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/remoteproc/
Dqcom,sc7280-mss-pil.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sc7280-mss-pil.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sibi Sankar <quic_sibis@quicinc.com>
19 - qcom,sc7280-mss-pil
23 - description: MSS QDSP6 registers
24 - description: RMB registers
26 reg-names:
28 - const: qdsp6
[all …]
Dqcom,msm8996-mss-pil.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,msm8996-mss-pil.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Sibi Sankar <quic_sibis@quicinc.com>
20 - qcom,msm8996-mss-pil
21 - qcom,msm8998-mss-pil
22 - qcom,sdm660-mss-pil
23 - qcom,sdm845-mss-pil
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/gt/uc/
Dintel_guc.h1 /* SPDX-License-Identifier: MIT */
3 * Copyright © 2014-2019 Intel Corporation
10 #include <linux/iosys-map.h>
28 * struct intel_guc - Top level structure of GuC.
36 /** @log: sub-structure containing GuC log related data and objects */
40 /** @slpc: sub-structure containing SLPC related data and objects */
42 /** @capture: the error-state-capture module's data and objects */
66 /* intel_guc_recv interrupt related state */
77 * responses related to GuC submission, used to determine if the GT is
82 /** @interrupts: pointers to GuC interrupt-managing functions. */
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dqcom,usb-hs-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,usb-hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
17 - qcom,usb-hs-phy-apq8064
18 - qcom,usb-hs-phy-msm8960
24 reset-names:
33 reset-names:
35 - const: phy
[all …]
Dbrcm,ns2-drd-phy.txt4 - compatible: brcm,ns2-drd-phy
5 - reg: offset and length of the NS2 PHY related registers.
6 - reg-names
8 icfg - for DRD ICFG configurations
9 rst-ctrl - for DRD IDM reset
10 crmu-ctrl - for CRMU core vdd, PHY and PHY PLL reset
11 usb2-strap - for port over current polarity reversal
12 - #phy-cells: Must be 0. No args required.
13 - vbus-gpios: vbus gpio binding
14 - id-gpios: id gpio binding
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dbrcm,ns2-drd-phy.txt4 - compatible: brcm,ns2-drd-phy
5 - reg: offset and length of the NS2 PHY related registers.
6 - reg-names
8 icfg - for DRD ICFG configurations
9 rst-ctrl - for DRD IDM reset
10 crmu-ctrl - for CRMU core vdd, PHY and PHY PLL reset
11 usb2-strap - for port over current polarity reversal
12 - #phy-cells: Must be 0. No args required.
13 - vbus-gpios: vbus gpio binding
14 - id-gpios: id gpio binding
[all …]
/kernel/linux/linux-6.6/drivers/usb/gadget/udc/cdns2/
Dcdns2-gadget.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * USBHS-DEV device controller driver header file
14 #include <linux/dma-direction.h>
22 * struct cdns2_ep0_regs - endpoint 0 related registers.
45 /* EP0CS - bitmasks. */
59 /* EP0FIFO - bitmasks. */
70 * struct cdns2_epx_base - base endpoint registers.
87 /* rxcon/txcon - endpoint control register bitmasks. */
88 /* Endpoint buffering: 0 - single buffering ... 3 - quad buffering. */
106 /* rxcs/txcs - endpoint control and status bitmasks. */
[all …]

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