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/kernel/linux/linux-5.10/include/kvm/
Darm_vgic.h97 struct kvm_vcpu *vcpu; /* SGIs and PPIs: The VCPU
123 u8 source; /* GICv2 SGIs only */
124 u8 active_source; /* GICv2 SGIs only */
234 /* Wants SGIs without active state */
/kernel/linux/linux-6.6/include/kvm/
Darm_vgic.h122 struct kvm_vcpu *vcpu; /* SGIs and PPIs: The VCPU
148 u8 source; /* GICv2 SGIs only */
149 u8 active_source; /* GICv2 SGIs only */
258 /* Wants SGIs without active state */
/kernel/linux/linux-5.10/arch/arm64/kvm/vgic/
Dvgic-mmio-v3.c121 /* Not a GICv4.1? No HW SGIs */ in vgic_mmio_write_v3_misc()
131 /* Switching HW SGIs? */ in vgic_mmio_write_v3_misc()
166 /* Not a GICv4.1? No HW SGIs */ in vgic_mmio_uaccess_write_v3_misc()
529 * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
968 * @allow_group1: Does the sysreg access allow generation of G1 SGIs
970 * With GICv3 (and ARE=1) CPUs trigger SGIs by writing to a system register.
1029 * An access targeting Group0 SGIs can only generate in vgic_v3_dispatch_sgi()
1030 * those, while an access targeting Group1 SGIs can in vgic_v3_dispatch_sgi()
Dvgic.c93 /* SGIs and PPIs */ in vgic_get_irq()
596 /* SGIs and LPIs cannot be wired up to any device */ in kvm_vgic_set_owner()
772 /* GICv2 SGIs can count for more than one... */ in compute_ap_list_depth()
804 * If we have multi-SGIs in the pipeline, we need to in vgic_flush_lr_state()
Dvgic-init.c199 * Enable and configure all SGIs to be edge-triggered and in kvm_vgic_vcpu_init()
212 /* SGIs */ in kvm_vgic_vcpu_init()
Dvgic-mmio.c342 * GICv2 SGIs are terribly broken. We can't restore in vgic_uaccess_write_spending()
434 * More fun with GICv2 SGIs! If we're clearing one of them in vgic_uaccess_write_cpending()
738 * The configuration cannot be changed for SGIs in general, in vgic_mmio_write_config()
/kernel/linux/linux-6.6/arch/arm64/kvm/vgic/
Dvgic-mmio-v3.c121 /* Not a GICv4.1? No HW SGIs */ in vgic_mmio_write_v3_misc()
131 /* Switching HW SGIs? */ in vgic_mmio_write_v3_misc()
180 /* Not a GICv4.1? No HW SGIs */ in vgic_mmio_uaccess_write_v3_misc()
599 * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
1082 * @allow_group1: Does the sysreg access allow generation of G1 SGIs
1084 * With GICv3 (and ARE=1) CPUs trigger SGIs by writing to a system register.
1143 * An access targeting Group0 SGIs can only generate in vgic_v3_dispatch_sgi()
1144 * those, while an access targeting Group1 SGIs can in vgic_v3_dispatch_sgi()
Dvgic.c95 /* SGIs and PPIs */ in vgic_get_irq()
612 /* SGIs and LPIs cannot be wired up to any device */ in kvm_vgic_set_owner()
788 /* GICv2 SGIs can count for more than one... */ in compute_ap_list_depth()
820 * If we have multi-SGIs in the pipeline, we need to in vgic_flush_lr_state()
Dvgic-init.c208 * Enable and configure all SGIs to be edge-triggered and in kvm_vgic_vcpu_init()
221 /* SGIs */ in kvm_vgic_vcpu_init()
Dvgic-mmio.c361 * GICv2 SGIs are terribly broken. We can't restore in vgic_uaccess_write_spending()
453 * More fun with GICv2 SGIs! If we're clearing one of them in vgic_uaccess_write_cpending()
760 * The configuration cannot be changed for SGIs in general, in vgic_mmio_write_config()
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Darm,gic.yaml17 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
19 have PPIs or SGIs.
Dti,omap4-wugen-mpu20 - Only SPIs can use the WUGEN as an interrupt parent. SGIs and PPIs
Dnvidia,tegra20-ictlr.txt27 - Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/
Dti,omap4-wugen-mpu20 - Only SPIs can use the WUGEN as an interrupt parent. SGIs and PPIs
Darm,gic.yaml17 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
19 have PPIs or SGIs.
Dnvidia,tegra20-ictlr.txt27 - Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs
/kernel/linux/linux-6.6/drivers/irqchip/
Dirq-hip04.c122 /* Interrupt configuration for SGIs can't be changed */ in hip04_irq_set_type()
329 /* Get the interrupt number and add 16 to skip over SGIs */ in hip04_irq_domain_xlate()
Dirq-gic-common.c112 * Deactivate and disable all SPIs. Leave the PPI and SGIs in gic_dist_config()
Dirq-alpine-msi.c35 u32 num_spis; /* The number of SGIs for MSIs */
Dirq-gic.c300 /* Interrupt configuration for SGIs can't be changed */ in gic_set_type()
368 * works because we don't nest SGIs... in gic_handle_irq()
1003 * Now let's migrate and clear any potential SGIs that might be in gic_migrate_target()
1010 * for previously sent SGIs by us to other CPUs either. in gic_migrate_target()
/kernel/linux/linux-5.10/drivers/irqchip/
Dirq-hip04.c122 /* Interrupt configuration for SGIs can't be changed */ in hip04_irq_set_type()
333 /* Get the interrupt number and add 16 to skip over SGIs */ in hip04_irq_domain_xlate()
Dirq-gic-common.c125 * Deactivate and disable all SPIs. Leave the PPI and SGIs in gic_dist_config()
Dirq-gic.c299 /* Interrupt configuration for SGIs can't be changed */ in gic_set_type()
367 * works because we don't nest SGIs... in gic_handle_irq()
973 * Now let's migrate and clear any potential SGIs that might be in gic_migrate_target()
980 * for previously sent SGIs by us to other CPUs either. in gic_migrate_target()
1218 * For primary GICs, skip over SGIs. in gic_init_bases()
Dirq-alpine-msi.c35 u32 num_spis; /* The number of SGIs for MSIs */
/kernel/linux/linux-6.6/tools/testing/selftests/kvm/lib/aarch64/
Dvgic.c113 "doesn't allow injecting SGIs. There's no mask for it."); in _kvm_arm_irq_line()

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