Searched full:smmuv2 (Results 1 – 6 of 6) sorted by relevance
98 For SMMUv2 implementations, there must be exactly one interrupt per
179 For SMMUv2 implementations, there must be exactly one interrupt per
191 #define ACPI_IORT_SMMU_V2 0x00000001 /* Generic SMMUv2 */195 #define ACPI_IORT_SMMU_CAVIUM_THUNDERX 0x00000005 /* Cavium thunder_x SMMUv2 */
127 | Cavium | ThunderX SMMUv2 | #27704 | N/A |
505 #define ACPI_IORT_SMMU_V2 0x00000001 /* Generic SMMUv2 */509 #define ACPI_IORT_SMMU_CAVIUM_THUNDERX 0x00000005 /* Cavium thunder_x SMMUv2 */
217 | Cavium | ThunderX SMMUv2 | #27704 | N/A |