| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/spi/ |
| D | spi-sifive.yaml | 4 $id: http://devicetree.org/schemas/spi/spi-sifive.yaml#
7 title: SiFive SPI controller
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
21 - sifive,fu540-c000-spi
22 - sifive,fu740-c000-spi
23 - const: sifive,spi0
26 Should be "sifive,<chip>-spi" and "sifive,spi<version>".
28 "sifive,fu540-c000-spi" and "sifive,fu740-c000-spi" for the SiFive SPI v0
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/ |
| D | spi-sifive.yaml | 4 $id: http://devicetree.org/schemas/spi/spi-sifive.yaml#
7 title: SiFive SPI controller
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
20 - const: sifive,fu540-c000-spi
21 - const: sifive,spi0
24 Should be "sifive,<chip>-spi" and "sifive,spi<version>".
26 "sifive,fu540-c000-spi" for the SiFive SPI v0 as integrated
27 onto the SiFive FU540 chip, and "sifive,spi0" for the SiFive
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pwm/ |
| D | pwm-sifive.yaml | 2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
8 title: SiFive PWM controller
11 - Paul Walmsley <paul.walmsley@sifive.com>
14 Unlike most other PWM controllers, the SiFive PWM controller currently
21 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
30 - sifive,fu540-c000-pwm
31 - sifive,fu740-c000-pwm
32 - const: sifive,pwm0
34 Should be "sifive,<chip>-pwm" and "sifive,pwm<version>". Supported
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pwm/ |
| D | pwm-sifive.yaml | 2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
8 title: SiFive PWM controller
11 - Yash Shah <yash.shah@sifive.com>
12 - Sagar Kadam <sagar.kadam@sifive.com>
13 - Paul Walmsley <paul.walmsley@sifive.com>
16 Unlike most other PWM controllers, the SiFive PWM controller currently
23 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
28 - const: sifive,fu540-c000-pwm
29 - const: sifive,pwm0
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/dma/ |
| D | sifive,fu540-c000-pdma.yaml | 4 $id: http://devicetree.org/schemas/dma/sifive,fu540-c000-pdma.yaml#
7 title: SiFive Unleashed Rev C000 Platform DMA
10 - Green Wan <green.wan@sifive.com>
11 - Palmer Debbelt <palmer@sifive.com>
12 - Paul Walmsley <paul.walmsley@sifive.com>
15 Platform DMA is a DMA engine of SiFive Unleashed. It supports 4
23 https://static.dev.sifive.com/FU540-C000-v1.0.pdf
32 - sifive,fu540-c000-pdma
33 - const: sifive,pdma0
35 Should be "sifive,<chip>-pdma" and "sifive,pdma<version>".
[all …]
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| /kernel/linux/linux-5.10/arch/riscv/boot/dts/sifive/ |
| D | fu540-c000.dtsi | 2 /* Copyright (c) 2018-2019 SiFive, Inc */
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
11 compatible = "sifive,fu540-c000", "sifive,fu540";
26 compatible = "sifive,e51", "sifive,rocket0", "riscv";
41 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
65 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
89 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
113 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
140 compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus";
144 compatible = "sifive,plic-1.0.0";
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/ |
| D | sifive,clint.yaml | 4 $id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
7 title: SiFive Core Local Interruptor
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
26 - const: sifive,fu540-c000-clint
27 - const: sifive,clint0
30 Should be "sifive,<chip>-clint" and "sifive,clint<version>".
32 "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated
33 onto the SiFive FU540 chip, and "sifive,clint0" for the SiFive
35 Please refer to sifive-blocks-ip-versioning.txt for details
53 compatible = "sifive,fu540-c000-clint", "sifive,clint0";
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/serial/ |
| D | sifive-serial.yaml | 4 $id: http://devicetree.org/schemas/serial/sifive-serial.yaml#
7 title: SiFive asynchronous serial interface (UART)
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
21 - sifive,fu540-c000-uart
22 - sifive,fu740-c000-uart
24 - const: sifive,uart0
27 Should be something similar to "sifive,<chip>-uart"
29 and "sifive,uart<version>" for the general UART IP
[all …]
|
| /kernel/linux/linux-6.6/arch/riscv/boot/dts/sifive/ |
| D | fu540-c000.dtsi | 2 /* Copyright (c) 2018-2019 SiFive, Inc */
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
11 compatible = "sifive,fu540-c000", "sifive,fu540";
26 compatible = "sifive,e51", "sifive,rocket0", "riscv";
41 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
65 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
89 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
113 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
167 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
181 compatible = "sifive,fu540-c000-prci";
[all …]
|
| D | fu740-c000.dtsi | 2 /* Copyright (c) 2020 SiFive, Inc */
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
11 compatible = "sifive,fu740-c000", "sifive,fu740";
26 compatible = "sifive,bullet0", "riscv";
42 compatible = "sifive,bullet0", "riscv";
66 compatible = "sifive,bullet0", "riscv";
90 compatible = "sifive,bullet0", "riscv";
114 compatible = "sifive,bullet0", "riscv";
170 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
182 compatible = "sifive,fu740-c000-prci";
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/serial/ |
| D | sifive-serial.yaml | 4 $id: http://devicetree.org/schemas/serial/sifive-serial.yaml#
7 title: SiFive asynchronous serial interface (UART)
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
20 - const: sifive,fu540-c000-uart
21 - const: sifive,uart0
24 Should be something similar to "sifive,<chip>-uart"
26 and "sifive,uart<version>" for the general UART IP
32 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/uart
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/sifive/ |
| D | sifive-blocks-ip-versioning.txt | 1 DT compatible string versioning for SiFive open-source IP blocks
4 strings for open-source SiFive IP blocks. HDL for these IP blocks
7 https://github.com/sifive/sifive-blocks
10 in the form "sifive,<ip-block-name><integer version number>".
12 An example is "sifive,uart0" from:
14 https://github.com/sifive/sifive-blocks/blob/v1.0/src/main/scala/devices/uart/UART.scala#L43
23 "sifive,uart0" to indicate that their driver is compatible with the
25 upstream sifive-blocks commits. It is expected that most drivers will
30 "sifive,fu540-c000-uart". This way, if SoC-specific
33 IP block-specific compatible string (such as "sifive,uart0") should
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/sifive/ |
| D | sifive-blocks-ip-versioning.txt | 1 DT compatible string versioning for SiFive open-source IP blocks
4 strings for open-source SiFive IP blocks. HDL for these IP blocks
7 https://github.com/sifive/sifive-blocks
10 in the form "sifive,<ip-block-name><integer version number>".
12 An example is "sifive,uart0" from:
14 https://github.com/sifive/sifive-blocks/blob/v1.0/src/main/scala/devices/uart/UART.scala#L43
23 "sifive,uart0" to indicate that their driver is compatible with the
25 upstream sifive-blocks commits. It is expected that most drivers will
30 "sifive,fu540-c000-uart". This way, if SoC-specific
33 IP block-specific compatible string (such as "sifive,uart0") should
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/cache/ |
| D | sifive,ccache0.yaml | 2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/cache/sifive,ccache0.yaml#
8 title: SiFive Composable Cache Controller
11 - Paul Walmsley <paul.walmsley@sifive.com>
14 The SiFive Composable Cache Controller is used to provide access to fast copies
24 - sifive,ccache0
25 - sifive,fu540-c000-ccache
26 - sifive,fu740-c000-ccache
36 - sifive,ccache0
37 - sifive,fu540-c000-ccache
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/timer/ |
| D | sifive,clint.yaml | 4 $id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
7 title: SiFive Core Local Interruptor
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
25 compatible with SiFive ones.
33 - sifive,fu540-c000-clint # SiFive FU540
36 - const: sifive,clint0 # SiFive CLINT v0 IP block
43 - const: sifive,clint0
49 Should be "<vendor>,<chip>-clint", followed by "sifive,clint<version>"
50 when compatible with a SiFive CLINT. Please refer to
51 sifive-blocks-ip-versioning.txt for details regarding the latter.
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/riscv/ |
| D | sifive.yaml | 4 $id: http://devicetree.org/schemas/riscv/sifive.yaml#
7 title: SiFive SoC-based boards
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
14 SiFive SoC-based boards
23 - sifive,hifive-unleashed-a00
24 - const: sifive,fu540-c000
25 - const: sifive,fu540
29 - sifive,hifive-unmatched-a00
30 - const: sifive,fu740-c000
[all …]
|
| D | cpus.yaml | 10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
37 - sifive,bullet0
38 - sifive,e5
39 - sifive,e7
40 - sifive,e71
41 - sifive,rocket0
42 - sifive,s7
43 - sifive,u5
44 - sifive,u54
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/gpio/ |
| D | sifive,gpio.yaml | 4 $id: http://devicetree.org/schemas/gpio/sifive,gpio.yaml#
7 title: SiFive GPIO controller
10 - Paul Walmsley <paul.walmsley@sifive.com>
16 - sifive,fu540-c000-gpio
17 - sifive,fu740-c000-gpio
19 - const: sifive,gpio0
44 It is 16 for the SiFive SoCs and 32 for the Canaan K210.
69 - sifive,fu540-c000-gpio
70 - sifive,fu740-c000-gpio
79 #include <dt-bindings/clock/sifive-fu540-prci.h>
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | sifive,plic-1.0.0.yaml | 2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
33 "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
35 SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
38 - Sagar Kadam <sagar.kadam@sifive.com>
39 - Paul Walmsley <paul.walmsley@sifive.com>
45 - const: sifive,fu540-c000-plic
46 - const: sifive,plic-1.0.0
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/riscv/ |
| D | sifive.yaml | 4 $id: http://devicetree.org/schemas/riscv/sifive.yaml#
7 title: SiFive SoC-based boards
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
14 SiFive SoC-based boards
22 - sifive,hifive-unleashed-a00
23 - const: sifive,fu540-c000
24 - const: sifive,fu540
|
| D | sifive-l2-cache.yaml | 2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml#
8 title: SiFive L2 Cache Controller
11 - Sagar Kadam <sagar.kadam@sifive.com>
12 - Yash Shah <yash.shah@sifive.com>
13 - Paul Walmsley <paul.walmsley@sifive.com>
16 The SiFive Level 2 Cache Controller is used to provide access to fast copies
29 - sifive,fu540-c000-ccache
37 - const: sifive,fu540-c000-ccache
85 compatible = "sifive,fu540-c000-ccache", "cache";
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/dma/ |
| D | sifive,fu540-c000-pdma.yaml | 4 $id: http://devicetree.org/schemas/dma/sifive,fu540-c000-pdma.yaml#
7 title: SiFive Unleashed Rev C000 Platform DMA
10 - Green Wan <green.wan@sifive.com>
11 - Palmer Debbelt <palmer@sifive.com>
12 - Paul Walmsley <paul.walmsley@sifive.com>
15 Platform DMA is a DMA engine of SiFive Unleashed. It supports 4
23 https://static.dev.sifive.com/FU540-C000-v1.0.pdf
28 - const: sifive,fu540-c000-pdma
51 compatible = "sifive,fu540-c000-pdma";
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/gpio/ |
| D | sifive,gpio.yaml | 4 $id: http://devicetree.org/schemas/gpio/sifive,gpio.yaml#
7 title: SiFive GPIO controller
10 - Yash Shah <yash.shah@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
16 - const: sifive,fu540-c000-gpio
17 - const: sifive,gpio0
55 #include <dt-bindings/clock/sifive-fu540-prci.h>
57 compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/ |
| D | sifive,plic-1.0.0.yaml | 2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
39 "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
41 SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
43 The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
48 - Paul Walmsley <paul.walmsley@sifive.com>
61 - sifive,fu540-c000-plic
64 - const: sifive,plic-1.0.0
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/sifive/ |
| D | fu540-prci.yaml | 2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/clock/sifive/fu540-prci.yaml#
8 title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI)
11 - Sagar Kadam <sagar.kadam@sifive.com>
12 - Paul Walmsley <paul.walmsley@sifive.com>
18 macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.
27 const: sifive,fu540-c000-prci
56 compatible = "sifive,fu540-c000-prci";
|