Searched +full:soc +full:- +full:specific (Results 1 – 25 of 1079) sorted by relevance
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| /kernel/linux/linux-5.10/drivers/gpu/drm/rockchip/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
15 Choose this option if you have a Rockchip soc chipset.
19 IP found on the SoC.
24 bool "Rockchip specific extensions for Analogix DP driver"
26 This selects support for Rockchip SoC specific extensions
28 on RK3288 or RK3399 based SoC, you should select this option.
34 This selects support for Rockchip SoC specific extensions
36 RK3399 based SoC, you should select this
40 bool "Rockchip specific extensions for Synopsys DW HDMI"
42 This selects support for Rockchip SoC specific extensions
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| /kernel/linux/linux-6.6/drivers/gpu/drm/rockchip/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
16 Choose this option if you have a Rockchip soc chipset.
20 IP found on the SoC.
38 bool "Rockchip specific extensions for Analogix DP driver"
43 This selects support for Rockchip SoC specific extensions
45 on RK3288 or RK3399 based SoC, you should select this option.
53 This selects support for Rockchip SoC specific extensions
55 RK3399 based SoC, you should select this
59 bool "Rockchip specific extensions for Synopsys DW HDMI"
61 This selects support for Rockchip SoC specific extensions
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| /kernel/linux/linux-6.6/drivers/net/ethernet/stmicro/stmmac/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "STMicroelectronics Multi-Gigabit Ethernet driver"
34 This selects the platform specific bus support for the stmmac driver.
45 tristate "Support for snps,dwc-qos-ethernet.txt DT binding."
50 Support for chips using the snps,dwc-qos-ethernet.txt DT binding.
57 platform specific code to function or is using platform
67 This selects the Anarion SoC glue layer support for the stmmac driver.
89 This selects the IPQ806x SoC glue layer support for the stmmac
91 acceleration features available on this SoC. Network devices
92 will behave like standard non-accelerated ethernet interfaces.
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| /kernel/linux/linux-6.6/Documentation/process/ |
| D | maintainer-soc.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 SoC Subsystem
8 --------
10 The SoC subsystem is a place of aggregation for SoC-specific code.
13 * devicetrees for 32- & 64-bit ARM and RISC-V
14 * 32-bit ARM board files (arch/arm/mach*)
15 * 32- & 64-bit ARM defconfigs
16 * SoC-specific drivers across architectures, in particular for 32- & 64-bit
17 ARM, RISC-V and Loongarch
19 These "SoC-specific drivers" do not include clock, GPIO etc drivers that have
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| /kernel/linux/linux-6.6/drivers/pci/controller/dwc/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 menu "DesignWare-based PCIe controllers"
27 required only for DT-based platforms. ACPI platforms with the
38 and therefore the driver re-uses the DesignWare core functions to
45 bool "Axis ARTPEC-6 PCIe controller (host mode)"
51 Enables support for the PCIe controller in the ARTPEC-6 SoC to work in
55 bool "Axis ARTPEC-6 PCIe controller (endpoint mode)"
61 Enables support for the PCIe controller in the ARTPEC-6 SoC to work in
65 tristate "Baikal-T1 PCIe controller"
70 Enables support for the PCIe controller in the Baikal-T1 SoC to work
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| /kernel/linux/linux-6.6/arch/arm/mach-omap2/ |
| D | cm.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc.
6 * Copyright (C) 2007-2009 Nokia Corporation
25 #include "prcm-common.h"
45 * struct cm_ll_data - fn ptrs to per-SoC CM function implementations
46 * @split_idlest_reg: ptr to the SoC CM-specific split_idlest_reg impl
47 * @wait_module_ready: ptr to the SoC CM-specific wait_module_ready impl
48 * @wait_module_idle: ptr to the SoC CM-specific wait_module_idle impl
49 * @module_enable: ptr to the SoC CM-specific module_enable impl
50 * @module_disable: ptr to the SoC CM-specific module_disable impl
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| /kernel/linux/linux-5.10/arch/arm/mach-omap2/ |
| D | cm.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc.
6 * Copyright (C) 2007-2009 Nokia Corporation
25 #include "prcm-common.h"
46 * struct cm_ll_data - fn ptrs to per-SoC CM function implementations
47 * @split_idlest_reg: ptr to the SoC CM-specific split_idlest_reg impl
48 * @wait_module_ready: ptr to the SoC CM-specific wait_module_ready impl
49 * @wait_module_idle: ptr to the SoC CM-specific wait_module_idle impl
50 * @module_enable: ptr to the SoC CM-specific module_enable impl
51 * @module_disable: ptr to the SoC CM-specific module_disable impl
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| /kernel/linux/linux-5.10/drivers/pci/controller/dwc/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
31 Enables support for the PCIe controller in the DRA7xx SoC to work in
34 host-specific features PCI_DRA7XX_HOST must be selected and in order
35 to enable device-specific features PCI_DRA7XX_EP must be selected.
46 Enables support for the PCIe controller in the DRA7xx SoC to work in
49 host-specific features PCI_DRA7XX_HOST must be selected and in order
50 to enable device-specific features PCI_DRA7XX_EP must be selected.
57 bool "Platform bus based DesignWare PCIe Controller - Host mode"
66 host-specific features PCIE_DW_PLAT_HOST must be selected and in
67 order to enable device-specific features PCI_DW_PLAT_EP must be
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| /kernel/linux/linux-5.10/drivers/net/ethernet/stmicro/stmmac/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "STMicroelectronics Multi-Gigabit Ethernet driver"
34 This selects the platform specific bus support for the stmmac driver.
45 tristate "Support for snps,dwc-qos-ethernet.txt DT binding."
50 Support for chips using the snps,dwc-qos-ethernet.txt DT binding.
57 platform specific code to function or is using platform
67 This selects the Anarion SoC glue layer support for the stmmac driver.
77 This selects the IPQ806x SoC glue layer support for the stmmac
79 acceleration features available on this SoC. Network devices
80 will behave like standard non-accelerated ethernet interfaces.
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/ |
| D | marvell,mvebu-pinctrl.txt | 1 * Marvell SoC pinctrl core driver for mpp
3 The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
4 (mpp) to a specific function. For each SoC family there is a SoC specific
7 Please refer to pinctrl-bindings.txt in this directory for details of the
11 A Marvell SoC pin configuration node is a node of a group of pins which can
12 be used for a specific device or function. Each node requires one or more
16 - compatible: "marvell,<soc>-pinctrl"
17 Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.
20 - marvell,pins: string array of mpp pins or group of pins to be muxed.
21 - marvell,function: string representing a function to mux to for all
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| D | fsl,imx-pinctrl.txt | 10 Please refer to pinctrl-bindings.txt in this directory for details of the
15 used for a specific device or function. This node represents both mux and config
18 such as pull-up, open drain, drive strength, etc.
21 - compatible: "fsl,<soc>-iomuxc"
22 Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
25 - fsl,pins: each entry consists of 6 integers and represents the mux and config
28 imx*-pinfunc.h under device tree source folder. The last integer CONFIG is
29 the pad setting value like pull-up on this pin. And that's why fsl,pins entry
41 Please refer to each fsl,<soc>-pinctrl,txt binding doc for SoC specific part
45 Some requirements for using fsl,imx-pinctrl binding:
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/ |
| D | marvell,mvebu-pinctrl.txt | 1 * Marvell SoC pinctrl core driver for mpp
3 The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
4 (mpp) to a specific function. For each SoC family there is a SoC specific
7 Please refer to pinctrl-bindings.txt in this directory for details of the
11 A Marvell SoC pin configuration node is a node of a group of pins which can
12 be used for a specific device or function. Each node requires one or more
16 - compatible: "marvell,<soc>-pinctrl"
17 Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.
20 - marvell,pins: string array of mpp pins or group of pins to be muxed.
21 - marvell,function: string representing a function to mux to for all
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| D | fsl,imx-pinctrl.txt | 10 Please refer to pinctrl-bindings.txt in this directory for details of the
15 used for a specific device or function. This node represents both mux and config
18 such as pull-up, open drain, drive strength, etc.
21 - compatible: "fsl,<soc>-iomuxc"
22 Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
25 - fsl,pins: each entry consists of 6 integers and represents the mux and config
28 imx*-pinfunc.h under device tree source folder. The last integer CONFIG is
29 the pad setting value like pull-up on this pin. And that's why fsl,pins entry
41 Please refer to each fsl,<soc>-pinctrl,txt binding doc for SoC specific part
45 Some requirements for using fsl,imx-pinctrl binding:
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mmc/ |
| D | bluefield-dw-mshc.txt | 1 * Mellanox Bluefield SoC specific extensions to the Synopsys Designware
4 Read synopsys-dw-mshc.txt for more details
7 a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
9 by synopsys-dw-mshc.txt and the properties used by the Mellanox Bluefield SoC
10 specific extensions to the Synopsys Designware Mobile Storage Host Controller.
15 - "mellanox,bluefield-dw-mshc": for controllers with Mellanox Bluefield SoC
16 specific extensions.
20 /* Mellanox Bluefield SoC MMC */
22 compatible = "mellanox,bluefield-dw-mshc";
25 fifo-depth = <0x100>;
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | bluefield-dw-mshc.txt | 1 * Mellanox Bluefield SoC specific extensions to the Synopsys Designware
4 Read synopsys-dw-mshc.txt for more details
7 a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
9 by synopsys-dw-mshc.txt and the properties used by the Mellanox Bluefield SoC
10 specific extensions to the Synopsys Designware Mobile Storage Host Controller.
15 - "mellanox,bluefield-dw-mshc": for controllers with Mellanox Bluefield SoC
16 specific extensions.
20 /* Mellanox Bluefield SoC MMC */
22 compatible = "mellanox,bluefield-dw-mshc";
25 fifo-depth = <0x100>;
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| D | samsung-sdhci.txt | 8 Required SoC Specific Properties:
9 - compatible: should be one of the following
10 - "samsung,s3c6410-sdhci": For controllers compatible with s3c6410 sdhci
12 - "samsung,exynos4210-sdhci": For controllers compatible with Exynos4 sdhci
15 Required Board Specific Properties:
16 - pinctrl-0: Should specify pin control groups used for this controller.
17 - pinctrl-names: Should contain only one value - "default".
21 compatible = "samsung,exynos4210-sdhci";
24 bus-width = <4>;
25 cd-gpios = <&gpk2 2 0>;
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| D | exynos-dw-mshc.txt | 1 * Samsung Exynos specific extensions to the Synopsys Designware Mobile
5 a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
7 by synopsys-dw-mshc.txt and the properties used by the Samsung Exynos specific
13 - "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210
14 specific extensions.
15 - "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412
16 specific extensions.
17 - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
18 specific extensions.
19 - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
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| /kernel/linux/linux-6.6/drivers/pinctrl/nomadik/ |
| D | pinctrl-abx500.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
34 * struct abx500_function - ABx500 pinctrl mux function
46 * struct abx500_pingroup - describes a ABx500 pin group
47 * @name: the name of this specific pin group
49 * from the driver-local pin enumeration space
73 #define UNUSED -1
85 * function between the ABx500 SOC family when using
109 * struct abx500_gpio_irq_cluster - indicates GPIOs which are interrupt
116 * read-in values into the cluster information table
126 * struct abx500_pinrange - map pin numbers to GPIO offsets
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| /kernel/linux/linux-5.10/drivers/pinctrl/nomadik/ |
| D | pinctrl-abx500.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
30 * struct abx500_function - ABx500 pinctrl mux function
42 * struct abx500_pingroup - describes a ABx500 pin group
43 * @name: the name of this specific pin group
45 * from the driver-local pin enumeration space
69 #define UNUSED -1
81 * function between the ABx500 SOC family when using
105 * struct abx500_gpio_irq_cluster - indicates GPIOs which are interrupt
112 * read-in values into the cluster information table
122 * struct abx500_pinrange - map pin numbers to GPIO offsets
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/sifive/ |
| D | sifive-blocks-ip-versioning.txt | 1 DT compatible string versioning for SiFive open-source IP blocks
4 strings for open-source SiFive IP blocks. HDL for these IP blocks
7 https://github.com/sifive/sifive-blocks
9 IP block-specific DT compatible strings are contained within the HDL,
10 in the form "sifive,<ip-block-name><integer version number>".
14 https://github.com/sifive/sifive-blocks/blob/v1.0/src/main/scala/devices/uart/UART.scala#L43
17 auto-discovery, the maintainers of these IP blocks intend to increment
25 upstream sifive-blocks commits. It is expected that most drivers will
26 match on these IP block-specific compatible strings.
28 DT data authors, when writing data for a particular SoC, should
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/sifive/ |
| D | sifive-blocks-ip-versioning.txt | 1 DT compatible string versioning for SiFive open-source IP blocks
4 strings for open-source SiFive IP blocks. HDL for these IP blocks
7 https://github.com/sifive/sifive-blocks
9 IP block-specific DT compatible strings are contained within the HDL,
10 in the form "sifive,<ip-block-name><integer version number>".
14 https://github.com/sifive/sifive-blocks/blob/v1.0/src/main/scala/devices/uart/UART.scala#L43
17 auto-discovery, the maintainers of these IP blocks intend to increment
25 upstream sifive-blocks commits. It is expected that most drivers will
26 match on these IP block-specific compatible strings.
28 DT data authors, when writing data for a particular SoC, should
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| /kernel/linux/linux-6.6/Documentation/arch/arm/spear/ |
| D | overview.rst | 6 ------------
11 The ST Microelectronics SPEAr range of ARM9/CortexA9 System-on-Chip CPUs are
19 - SPEAr3XX (3XX SOC series, based on ARM9)
20 - SPEAr300 (SOC)
21 - SPEAr300 Evaluation Board
22 - SPEAr310 (SOC)
23 - SPEAr310 Evaluation Board
24 - SPEAr320 (SOC)
25 - SPEAr320 Evaluation Board
26 - SPEAr6XX (6XX SOC series, based on ARM9)
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| /kernel/linux/linux-5.10/Documentation/arm/spear/ |
| D | overview.rst | 6 ------------
11 The ST Microelectronics SPEAr range of ARM9/CortexA9 System-on-Chip CPUs are
19 - SPEAr3XX (3XX SOC series, based on ARM9)
20 - SPEAr300 (SOC)
21 - SPEAr300 Evaluation Board
22 - SPEAr310 (SOC)
23 - SPEAr310 Evaluation Board
24 - SPEAr320 (SOC)
25 - SPEAr320 Evaluation Board
26 - SPEAr6XX (6XX SOC series, based on ARM9)
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| /kernel/linux/linux-5.10/drivers/thermal/samsung/ |
| D | exynos_tmu.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * exynos_tmu.c - Samsung Exynos TMU (Thermal Management Unit)
24 #include <dt-bindings/thermal/thermal_exynos.h>
44 /* Exynos3250 specific registers */
47 /* Exynos4210 specific registers */
51 /* Exynos5250, Exynos4412, Exynos3250 specific registers */
74 /* Exynos5260 specific */
80 /* Exynos4412 specific */
84 /* Exynos5433 specific registers */
107 /* Exynos7 specific registers */
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| /kernel/linux/linux-6.6/drivers/thermal/samsung/ |
| D | exynos_tmu.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * exynos_tmu.c - Samsung Exynos TMU (Thermal Management Unit)
25 #include <dt-bindings/thermal/thermal_exynos.h>
43 /* Exynos3250 specific registers */
46 /* Exynos4210 specific registers */
50 /* Exynos5250, Exynos4412, Exynos3250 specific registers */
73 /* Exynos5260 specific */
79 /* Exynos4412 specific */
83 /* Exynos5433 specific registers */
106 /* Exynos7 specific registers */
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