| /kernel/linux/linux-6.6/Documentation/hwmon/ |
| D | lm93.rst | 10 Addresses scanned: I2C 0x2c-0x2e
18 Addresses scanned: I2C 0x2c-0x2e
24 - Mark M. Hoffman <mhoffman@lightlink.com>
25 - Ported to 2.6 by Eric J. Bowersox <ericb@aspsys.com>
26 - Adapted to 2.6.20 by Carsten Emde <ce@osadl.org>
27 - Modified for mainline integration by Hans J. Koch <hjk@hansjkoch.de>
30 -----------------
33 Set to non-zero to force some initializations (default is 0).
38 Configures in7 and in8 limit type, where 0 means absolute and non-zero
54 --------------------
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| D | drivetemp.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 ----------
10 ANS T13/1699-D
11 Information technology - AT Attachment 8 - ATA/ATAPI Command Set (ATA8-ACS)
14 Information technology - SCSI Primary Commands - 4 (SPC-4)
17 Information technology - SCSI / ATA Translation - 5 (SAT-5)
21 -----------
34 ----------
36 Reading the drive temperature may reset the spin down timer on some drives.
43 change its mode (meaning the drive will not spin up). It is unknown if other
[all …]
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| /kernel/linux/linux-5.10/Documentation/hwmon/ |
| D | lm93.rst | 10 Addresses scanned: I2C 0x2c-0x2e
18 Addresses scanned: I2C 0x2c-0x2e
24 - Mark M. Hoffman <mhoffman@lightlink.com>
25 - Ported to 2.6 by Eric J. Bowersox <ericb@aspsys.com>
26 - Adapted to 2.6.20 by Carsten Emde <ce@osadl.org>
27 - Modified for mainline integration by Hans J. Koch <hjk@hansjkoch.de>
30 -----------------
33 Set to non-zero to force some initializations (default is 0).
38 Configures in7 and in8 limit type, where 0 means absolute and non-zero
54 --------------------
[all …]
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| D | drivetemp.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 ----------
10 ANS T13/1699-D
11 Information technology - AT Attachment 8 - ATA/ATAPI Command Set (ATA8-ACS)
14 Information technology - SCSI Primary Commands - 4 (SPC-4)
17 Information technology - SCSI / ATA Translation - 5 (SAT-5)
21 -----------
34 ----------
36 Reading the drive temperature may reset the spin down timer on some drives.
43 change its mode (meaning the drive will not spin up). It is unknown if other
[all …]
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| /kernel/linux/linux-6.6/tools/testing/selftests/kvm/ |
| D | set_memory_region_test.c | 1 // SPDX-License-Identifier: GPL-2.0
56 struct kvm_run *run = vcpu->run; in vcpu_worker()
61 * Loop until the guest is done. Re-enter the guest on all MMIO exits, in vcpu_worker()
68 if (run->exit_reason == KVM_EXIT_IO) { in vcpu_worker()
77 if (run->exit_reason != KVM_EXIT_MMIO) in vcpu_worker()
80 TEST_ASSERT(!run->mmio.is_write, "Unexpected exit mmio write"); in vcpu_worker()
81 TEST_ASSERT(run->mmio.len == 8, in vcpu_worker()
82 "Unexpected exit mmio size = %u", run->mmio.len); in vcpu_worker()
84 TEST_ASSERT(run->mmio.phys_addr == MEM_REGION_GPA, in vcpu_worker()
86 run->mmio.phys_addr); in vcpu_worker()
[all …]
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| /kernel/linux/linux-5.10/tools/testing/selftests/kvm/ |
| D | set_memory_region_test.c | 1 // SPDX-License-Identifier: GPL-2.0
63 * Loop until the guest is done. Re-enter the guest on all MMIO exits, in vcpu_worker()
72 if (run->exit_reason == KVM_EXIT_IO) { in vcpu_worker()
81 if (run->exit_reason != KVM_EXIT_MMIO) in vcpu_worker()
84 TEST_ASSERT(!run->mmio.is_write, "Unexpected exit mmio write"); in vcpu_worker()
85 TEST_ASSERT(run->mmio.len == 8, in vcpu_worker()
86 "Unexpected exit mmio size = %u", run->mmio.len); in vcpu_worker()
88 TEST_ASSERT(run->mmio.phys_addr == MEM_REGION_GPA, in vcpu_worker()
90 run->mmio.phys_addr); in vcpu_worker()
91 memcpy(run->mmio.data, &MMIO_VAL, 8); in vcpu_worker()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/ |
| D | selftest_rps.c | 1 // SPDX-License-Identifier: MIT
22 #define CPU_LATENCY 0 /* -1 to disable pm_qos, 0 to disable cstates */
33 return -1; in cmp_u64()
45 return -1; in cmp_u32()
64 #define CS_GPR(x) GEN8_RING_CS_GPR(engine->mmio_base, x) in create_spin_counter()
72 obj = i915_gem_object_create_internal(vm->i915, 64 << 10); in create_spin_counter()
76 end = obj->base.size / sizeof(u32) - 1; in create_spin_counter()
109 loop = cs - base; in create_spin_counter()
122 *cs++ = lower_32_bits(vma->node.start + end * sizeof(*cs)); in create_spin_counter()
123 *cs++ = upper_32_bits(vma->node.start + end * sizeof(*cs)); in create_spin_counter()
[all …]
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| D | selftest_engine_pm.c | 2 * SPDX-License-Identifier: GPL-2.0
19 struct igt_spinner spin; in live_engine_busy_stats() local
23 * Check that if an engine supports busy-stats, they tell the truth. in live_engine_busy_stats()
26 if (igt_spinner_init(&spin, gt)) in live_engine_busy_stats()
27 return -ENOMEM; in live_engine_busy_stats()
42 err = -EBUSY; in live_engine_busy_stats()
57 engine->name, in live_engine_busy_stats()
60 err = -EINVAL; in live_engine_busy_stats()
65 rq = igt_spinner_create_request(&spin, in live_engine_busy_stats()
66 engine->kernel_context, in live_engine_busy_stats()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/gt/ |
| D | selftest_rps.c | 1 // SPDX-License-Identifier: MIT
26 #define CPU_LATENCY 0 /* -1 to disable pm_qos, 0 to disable cstates */
37 return -1; in cmp_u64()
49 return -1; in cmp_u32()
68 #define CS_GPR(x) GEN8_RING_CS_GPR(engine->mmio_base, x) in create_spin_counter()
76 obj = i915_gem_object_create_internal(vm->i915, 64 << 10); in create_spin_counter()
80 end = obj->base.size / sizeof(u32) - 1; in create_spin_counter()
113 loop = cs - base; in create_spin_counter()
134 GEM_BUG_ON(cs - base > end); in create_spin_counter()
190 mutex_lock(&rps->lock); in rps_set_check()
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| D | selftest_engine_pm.c | 1 // SPDX-License-Identifier: GPL-2.0
25 return *a - *b; in cmp_u64()
76 struct intel_engine_cs *engine = ce->engine; in __measure_timestamps()
77 u32 *sema = memset32(engine->status_page.addr + 1000, 0, 5); in __measure_timestamps()
78 u32 offset = i915_ggtt_offset(engine->status_page.vma); in __measure_timestamps()
96 cs = emit_srm(cs, RING_TIMESTAMP(engine->mmio_base), offset + 4000); in __measure_timestamps()
97 cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4004); in __measure_timestamps()
102 cs = emit_srm(cs, RING_TIMESTAMP(engine->mmio_base), offset + 4016); in __measure_timestamps()
103 cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4012); in __measure_timestamps()
117 while (READ_ONCE(sema[1]) == 0) /* wait for the gpu to catch up */ in __measure_timestamps()
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| /kernel/linux/linux-5.10/drivers/of/unittest-data/ |
| D | overlay.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
9 hvac_2: hvac-large-1 {
10 compatible = "ot,hvac-large";
11 heat-range = < 40 75 >;
12 cool-range = < 65 80 >;
18 #address-cells = <1>;
19 #size-cells = <1>;
23 #address-cells = <1>;
24 #size-cells = <1>;
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| /kernel/linux/linux-6.6/drivers/of/unittest-data/ |
| D | overlay.dtso | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
8 hvac_2: hvac-large-1 {
9 compatible = "ot,hvac-large";
10 heat-range = <40 75>;
11 cool-range = <65 80>;
17 #address-cells = <1>;
18 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <1>;
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| /kernel/linux/linux-5.10/arch/sparc/include/asm/ |
| D | backoff.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 * completion of the compare-and-swap instruction. Heavily
14 * When an atomic operation fails and needs to be retried, we spin a
16 * operation we double the spin count, realizing an exponential
19 * When we spin, we try to use an operation that will cause the
24 * On all cpus prior to SPARC-T4 we do three dummy reads of the
28 * For SPARC-T4 and later we have a special "pause" instruction
31 * unless a disrupting trap happens first. SPARC-T4 specifically
39 * on earlier chips, we shift the backoff value up by 7 bits. (Three
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| /kernel/linux/linux-6.6/arch/sparc/include/asm/ |
| D | backoff.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 * completion of the compare-and-swap instruction. Heavily
14 * When an atomic operation fails and needs to be retried, we spin a
16 * operation we double the spin count, realizing an exponential
19 * When we spin, we try to use an operation that will cause the
24 * On all cpus prior to SPARC-T4 we do three dummy reads of the
28 * For SPARC-T4 and later we have a special "pause" instruction
31 * unless a disrupting trap happens first. SPARC-T4 specifically
39 * on earlier chips, we shift the backoff value up by 7 bits. (Three
|
| /kernel/linux/linux-5.10/kernel/locking/ |
| D | spinlock.c | 1 // SPDX-License-Identifier: GPL-2.0
10 * SMP and the DEBUG_SPINLOCK cases. (UP-nondebug inlines them)
33 * If lockdep is enabled then we use the non-preemption spin-ops
35 * not re-enabled during lock-acquire (which the preempt-spin-ops do):
63 * This could be a long-held lock. We both prepare to spin for a long
76 arch_##op##_relax(&lock->raw_lock); \
92 arch_##op##_relax(&lock->raw_lock); \
109 /* irq-disabling. We use the generic preemption-aware */ \
118 * Build preemption-friendly versions of the following
119 * lock-spinning functions:
[all …]
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| /kernel/linux/linux-5.10/arch/x86/include/asm/ |
| D | spinlock.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
16 * Simple spin lock operations. There are two variants, one clears IRQ's
19 * These are fair FIFO ticket locks, which support up to 2^16 CPUs.
24 /* How long a lock should spin before we consider blocking */
30 * Read-write spinlocks, allowing multiple readers
35 * can "mix" irq-safe locks - any writer needs to get a
36 * irq-safe write-lock, but readers can get non-irqsafe
37 * read-locks.
39 * On x86, we implement read-write locks using the generic qrwlock with
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| /kernel/linux/linux-6.6/arch/x86/include/asm/ |
| D | spinlock.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
16 * Simple spin lock operations. There are two variants, one clears IRQ's
19 * These are fair FIFO ticket locks, which support up to 2^16 CPUs.
24 /* How long a lock should spin before we consider blocking */
30 * Read-write spinlocks, allowing multiple readers
35 * can "mix" irq-safe locks - any writer needs to get a
36 * irq-safe write-lock, but readers can get non-irqsafe
37 * read-locks.
39 * On x86, we implement read-write locks using the generic qrwlock with
|
| /kernel/linux/linux-6.6/drivers/net/can/softing/ |
| D | softing_main.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2008-2010
5 * - Kurt Van Dijck, EIA Electronics
15 #define TX_ECHO_SKB_MAX (((TXMAX+1)/2)-1)
19 * is online (ie. up 'n running, not sleeping, not busoff
27 return (can->state <= CAN_STATE_ERROR_PASSIVE); in canif_is_active()
33 if (card->pdat->generation >= 2) { in softing_set_reset_dpram()
34 spin_lock_bh(&card->spin); in softing_set_reset_dpram()
35 iowrite8(ioread8(&card->dpram[DPRAM_V2_RESET]) & ~1, in softing_set_reset_dpram()
36 &card->dpram[DPRAM_V2_RESET]); in softing_set_reset_dpram()
[all …]
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| /kernel/linux/linux-5.10/drivers/net/can/softing/ |
| D | softing_main.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2008-2010
5 * - Kurt Van Dijck, EIA Electronics
14 #define TX_ECHO_SKB_MAX (((TXMAX+1)/2)-1)
18 * is online (ie. up 'n running, not sleeping, not busoff
26 return (can->state <= CAN_STATE_ERROR_PASSIVE); in canif_is_active()
32 if (card->pdat->generation >= 2) { in softing_set_reset_dpram()
33 spin_lock_bh(&card->spin); in softing_set_reset_dpram()
34 iowrite8(ioread8(&card->dpram[DPRAM_V2_RESET]) & ~1, in softing_set_reset_dpram()
35 &card->dpram[DPRAM_V2_RESET]); in softing_set_reset_dpram()
[all …]
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| /kernel/linux/linux-6.6/kernel/locking/ |
| D | spinlock.c | 1 // SPDX-License-Identifier: GPL-2.0
10 * SMP and the DEBUG_SPINLOCK cases. (UP-nondebug inlines them)
33 * If lockdep is enabled then we use the non-preemption spin-ops
35 * not re-enabled during lock-acquire (which the preempt-spin-ops do):
63 * This could be a long-held lock. We both prepare to spin for a long
76 arch_##op##_relax(&lock->raw_lock); \
92 arch_##op##_relax(&lock->raw_lock); \
109 /* irq-disabling. We use the generic preemption-aware */ \
118 * Build preemption-friendly versions of the following
119 * lock-spinning functions:
[all …]
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| /kernel/linux/linux-6.6/Documentation/locking/ |
| D | spinlocks.rst | 5 Lesson 1: Spin locks
20 there is only one thread-of-control within the region(s) protected by that
21 lock. This works well even under UP also, so the code does _not_ need to
22 worry about UP vs SMP issues: the spinlocks work correctly under both.
26 Documentation/memory-barriers.txt
33 spinlock for most things - using more than one spinlock can make things a
35 sequences that you **know** need to be split up: avoid it at all cost if you
45 NOTE! The spin-lock is safe only when you **also** use the lock itself
50 ----
52 Lesson 2: reader-writer spinlocks.
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| D | rt-mutex-design.rst | 2 RT-mutex implementation design
12 Documentation/locking/rt-mutex.rst. Although this document does explain problems
22 ----------------------------
49 A ---+
52 C +----+
54 B +-------->
59 -------------------------
74 -----------
80 - The PI chain is an ordered series of locks and processes that cause
86 - In this document, to differentiate from locks that implement
[all …]
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| /kernel/linux/linux-5.10/Documentation/locking/ |
| D | spinlocks.rst | 5 Lesson 1: Spin locks
20 there is only one thread-of-control within the region(s) protected by that
21 lock. This works well even under UP also, so the code does _not_ need to
22 worry about UP vs SMP issues: the spinlocks work correctly under both.
26 Documentation/memory-barriers.txt
33 spinlock for most things - using more than one spinlock can make things a
35 sequences that you **know** need to be split up: avoid it at all cost if you
45 NOTE! The spin-lock is safe only when you **also** use the lock itself
50 ----
52 Lesson 2: reader-writer spinlocks.
[all …]
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| D | rt-mutex-design.rst | 2 RT-mutex implementation design
12 Documentation/locking/rt-mutex.rst. Although this document does explain problems
22 ----------------------------
49 A ---+
52 C +----+
54 B +-------->
59 -------------------------
74 -----------
80 - The PI chain is an ordered series of locks and processes that cause
86 - In this document, to differentiate from locks that implement
[all …]
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| /kernel/linux/linux-6.6/arch/arc/include/asm/ |
| D | atomic-spinlock.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Non hardware assisted Atomic-R-M-W
8 * Locking would change to irq-disabling only (UP) and spinlocks (SMP)
25 WRITE_ONCE(v->counter, i); in arch_atomic_set()
37 v->counter c_op i; \
48 * spin lock/unlock provides the needed smp_mb() before/after \
51 temp = v->counter; \
53 v->counter = temp; \
66 * spin lock/unlock provides the needed smp_mb() before/after \
69 orig = v->counter; \
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