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/kernel/linux/linux-6.6/Documentation/hwmon/
Dnct6775.rst15 Addresses scanned: ISA address retrieved from Super I/O registers
19 * Nuvoton NCT5572D/NCT6771F/NCT6772F/NCT6775F/W83677HG-I
23 Addresses scanned: ISA address retrieved from Super I/O registers
31 Addresses scanned: ISA address retrieved from Super I/O registers
39 Addresses scanned: ISA address retrieved from Super I/O registers
47 Addresses scanned: ISA address retrieved from Super I/O registers
55 Addresses scanned: ISA address retrieved from Super I/O registers
63 Addresses scanned: ISA address retrieved from Super I/O registers
71 Addresses scanned: ISA address retrieved from Super I/O registers
79 Addresses scanned: ISA address retrieved from Super I/O registers
[all …]
Df71882fg.rst10 Addresses scanned: none, address read from Super I/O config space
18 Addresses scanned: none, address read from Super I/O config space
26 Addresses scanned: none, address read from Super I/O config space
34 Addresses scanned: none, address read from Super I/O config space
42 Addresses scanned: none, address read from Super I/O config space
50 Addresses scanned: none, address read from Super I/O config space
58 Addresses scanned: none, address read from Super I/O config space
66 Addresses scanned: none, address read from Super I/O config space
74 Addresses scanned: none, address read from Super I/O config space
82 Addresses scanned: none, address read from Super I/O config space
[all …]
Dit87.rst10 Addresses scanned: from Super I/O config space (8 I/O ports)
18 Addresses scanned: from Super I/O config space (8 I/O ports)
24 Addresses scanned: from Super I/O config space (8 I/O ports)
32 Addresses scanned: from Super I/O config space (8 I/O ports)
40 Addresses scanned: from Super I/O config space (8 I/O ports)
48 Addresses scanned: from Super I/O config space (8 I/O ports)
56 Addresses scanned: from Super I/O config space (8 I/O ports)
64 Addresses scanned: from Super I/O config space (8 I/O ports)
72 Addresses scanned: from Super I/O config space (8 I/O ports)
80 Addresses scanned: from Super I/O config space (8 I/O ports)
[all …]
Dw83627ehf.rst10 Addresses scanned: ISA address retrieved from Super I/O registers
18 Addresses scanned: ISA address retrieved from Super I/O registers
22 * Winbond W83627DHG-P
26 Addresses scanned: ISA address retrieved from Super I/O registers
34 Addresses scanned: ISA address retrieved from Super I/O registers
42 Addresses scanned: ISA address retrieved from Super I/O registers
46 * Winbond W83667HG-B
50 Addresses scanned: ISA address retrieved from Super I/O registers
54 * Nuvoton NCT6775F/W83667HG-I
58 Addresses scanned: ISA address retrieved from Super I/O registers
[all …]
Df71805f.rst10 Addresses scanned: none, address read from Super I/O config space
18 Addresses scanned: none, address read from Super I/O config space
26 Addresses scanned: none, address read from Super I/O config space
44 -----------
46 The Fintek F71805F/FG Super I/O chip includes complete hardware monitoring
53 The Fintek F71872F/FG Super I/O chip is almost the same, with two
57 The Fintek F71806F/FG Super-I/O chip is essentially the same as the
65 ------------------
67 Voltages are sampled by an 8-bit ADC with a LSB of 8 mV. The supported
84 in1 VIN1 VTT1.2V 10K - 1.00 1.20 V
[all …]
Dpc87427.rst10 Addresses scanned: none, address read from Super I/O config space
21 -----------
23 The National Semiconductor Super I/O chip includes complete hardware
36 --------------
38 Fan rotation speeds are reported as 14-bit values from a gated clock
41 An alarm is triggered if the rotation speed drops below a programmable
42 limit. Another alarm is triggered if the speed is too low to be measured
46 Fan Speed Control
47 -----------------
49 Fan speed can be controlled by PWM outputs. There are 4 possible modes:
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/usb/
Dusb.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
22 phy-names:
26 usb-phy:
27 $ref: /schemas/types.yaml#/definitions/phandle-array
36 UTMI+ PHY with an 8- or 16-bit interface if UTMI+ is selected, UTMI+ low
38 serial is specified and High-Speed Inter-Chip feature if HSIC is
44 maximum-speed:
[all …]
Dcdns,usb3.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence USBSS-DRD controller
10 - Pawel Laszczak <pawell@cadence.com>
18 - description: OTG controller registers
19 - description: XHCI Host controller registers
20 - description: DEVICE controller registers
22 reg-names:
24 - const: otg
[all …]
/kernel/linux/linux-5.10/Documentation/hwmon/
Dnct6775.rst15 Addresses scanned: ISA address retrieved from Super I/O registers
19 * Nuvoton NCT5572D/NCT6771F/NCT6772F/NCT6775F/W83677HG-I
23 Addresses scanned: ISA address retrieved from Super I/O registers
31 Addresses scanned: ISA address retrieved from Super I/O registers
39 Addresses scanned: ISA address retrieved from Super I/O registers
47 Addresses scanned: ISA address retrieved from Super I/O registers
55 Addresses scanned: ISA address retrieved from Super I/O registers
63 Addresses scanned: ISA address retrieved from Super I/O registers
71 Addresses scanned: ISA address retrieved from Super I/O registers
79 Addresses scanned: ISA address retrieved from Super I/O registers
[all …]
Df71882fg.rst10 Addresses scanned: none, address read from Super I/O config space
18 Addresses scanned: none, address read from Super I/O config space
26 Addresses scanned: none, address read from Super I/O config space
34 Addresses scanned: none, address read from Super I/O config space
42 Addresses scanned: none, address read from Super I/O config space
50 Addresses scanned: none, address read from Super I/O config space
58 Addresses scanned: none, address read from Super I/O config space
66 Addresses scanned: none, address read from Super I/O config space
74 Addresses scanned: none, address read from Super I/O config space
82 Addresses scanned: none, address read from Super I/O config space
[all …]
Dit87.rst10 Addresses scanned: from Super I/O config space (8 I/O ports)
18 Addresses scanned: from Super I/O config space (8 I/O ports)
24 Addresses scanned: from Super I/O config space (8 I/O ports)
32 Addresses scanned: from Super I/O config space (8 I/O ports)
40 Addresses scanned: from Super I/O config space (8 I/O ports)
48 Addresses scanned: from Super I/O config space (8 I/O ports)
56 Addresses scanned: from Super I/O config space (8 I/O ports)
64 Addresses scanned: from Super I/O config space (8 I/O ports)
72 Addresses scanned: from Super I/O config space (8 I/O ports)
80 Addresses scanned: from Super I/O config space (8 I/O ports)
[all …]
Dw83627ehf.rst10 Addresses scanned: ISA address retrieved from Super I/O registers
18 Addresses scanned: ISA address retrieved from Super I/O registers
22 * Winbond W83627DHG-P
26 Addresses scanned: ISA address retrieved from Super I/O registers
34 Addresses scanned: ISA address retrieved from Super I/O registers
42 Addresses scanned: ISA address retrieved from Super I/O registers
46 * Winbond W83667HG-B
50 Addresses scanned: ISA address retrieved from Super I/O registers
54 * Nuvoton NCT6775F/W83667HG-I
58 Addresses scanned: ISA address retrieved from Super I/O registers
[all …]
Df71805f.rst10 Addresses scanned: none, address read from Super I/O config space
18 Addresses scanned: none, address read from Super I/O config space
26 Addresses scanned: none, address read from Super I/O config space
44 -----------
46 The Fintek F71805F/FG Super I/O chip includes complete hardware monitoring
53 The Fintek F71872F/FG Super I/O chip is almost the same, with two
57 The Fintek F71806F/FG Super-I/O chip is essentially the same as the
65 ------------------
67 Voltages are sampled by an 8-bit ADC with a LSB of 8 mV. The supported
84 in1 VIN1 VTT1.2V 10K - 1.00 1.20 V
[all …]
Dpc87427.rst10 Addresses scanned: none, address read from Super I/O config space
21 -----------
23 The National Semiconductor Super I/O chip includes complete hardware
36 --------------
38 Fan rotation speeds are reported as 14-bit values from a gated clock
41 An alarm is triggered if the rotation speed drops below a programmable
42 limit. Another alarm is triggered if the speed is too low to be measured
46 Fan Speed Control
47 -----------------
49 Fan speed can be controlled by PWM outputs. There are 4 possible modes:
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dnvidia,tegra194-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
Dsocionext,uniphier-usb3ss-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3ss-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 Super-Speed (SS) PHY
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about Super-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro4-usb3-ssphy
22 - socionext,uniphier-pro5-usb3-ssphy
[all …]
/kernel/linux/linux-5.10/drivers/usb/gadget/function/
Du_uvc.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 * Copyright (c) 2013-2014 Samsung Electronics Co., Ltd.
32 * Control descriptors array pointers for full-/high-speed and
33 * super-speed. They point by default to the uvc_fs_control_cls and
41 * Streaming descriptors array pointers for full-speed, high-speed and
42 * super-speed. They will point to the uvc_[fhs]s_streaming_cls arrays
43 * for configfs-based gadgets. Legacy gadgets must initialize them in
50 /* Default control descriptors for configfs-based gadgets. */
57 * Control descriptors pointers arrays for full-/high-speed and
58 * super-speed. The first element is a configurable control header
[all …]
/kernel/linux/linux-6.6/drivers/usb/gadget/function/
Du_uvc.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 * Copyright (c) 2013-2014 Samsung Electronics Co., Ltd.
36 * Control descriptors array pointers for full-/high-speed and
37 * super-speed. They point by default to the uvc_fs_control_cls and
45 * Streaming descriptors array pointers for full-speed, high-speed and
46 * super-speed. They will point to the uvc_[fhs]s_streaming_cls arrays
47 * for configfs-based gadgets. Legacy gadgets must initialize them in
54 /* Default control descriptors for configfs-based gadgets. */
60 * Control descriptors pointers arrays for full-/high-speed and
61 * super-speed. The first element is a configurable control header
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/
Dgeneric.txt4 - maximum-speed: tells USB controllers we want to work up to a certain
5 speed. Valid arguments are "super-speed-plus",
6 "super-speed", "high-speed", "full-speed" and
7 "low-speed". In case this isn't passed via DT, USB
10 - dr_mode: tells Dual-Role USB controllers that we want to work on a
15 - phy_type: tells USB controllers that we want to configure the core to support
16 a UTMI+ PHY with an 8- or 16-bit interface if UTMI+ is
20 - otg-rev: tells usb driver the release number of the OTG and EH supplement
22 in binary-coded decimal (i.e. 2.0 is 0200H). This
24 is enabled, if ADP is required, otg-rev should be
[all …]
Dcdns,usb3.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence USBSS-DRD controller bindings
10 - Pawel Laszczak <pawell@cadence.com>
18 - description: OTG controller registers
19 - description: XHCI Host controller registers
20 - description: DEVICE controller registers
22 reg-names:
24 - const: otg
[all …]
/kernel/linux/linux-6.6/drivers/usb/common/
Dcommon.c1 // SPDX-License-Identifier: GPL-2.0
7 * compiled-in as well. Otherwise, if either of the two stacks is
30 * usb_ep_type_string() - Returns human readable-name of the endpoint type.
31 * @ep_type: The endpoint type to return human-readable name for. If it's not
71 [USB_SPEED_LOW] = "low-speed",
72 [USB_SPEED_FULL] = "full-speed",
73 [USB_SPEED_HIGH] = "high-speed",
75 [USB_SPEED_SUPER] = "super-speed",
76 [USB_SPEED_SUPER_PLUS] = "super-speed-plus",
81 [USB_SSP_GEN_2x1] = "super-speed-plus-gen2x1",
[all …]
/kernel/linux/linux-5.10/drivers/usb/common/
Dcommon.c1 // SPDX-License-Identifier: GPL-2.0
7 * compiled-in as well. Otherwise, if either of the two stacks is
29 * usb_ep_type_string() - Returns human readable-name of the endpoint type.
30 * @ep_type: The endpoint type to return human-readable name for. If it's not
70 [USB_SPEED_LOW] = "low-speed",
71 [USB_SPEED_FULL] = "full-speed",
72 [USB_SPEED_HIGH] = "high-speed",
74 [USB_SPEED_SUPER] = "super-speed",
75 [USB_SPEED_SUPER_PLUS] = "super-speed-plus",
80 [USB_SSP_GEN_2x1] = "super-speed-plus-gen2x1",
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dsocionext,uniphier-usb3ss-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3ss-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 Super-Speed (SS) PHY
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about Super-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro4-usb3-ssphy
22 - socionext,uniphier-pro5-usb3-ssphy
[all …]
Dnvidia,tegra124-xusb-padctl.txt11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
34 --------------------
35 - compatible: Must be:
[all …]
/kernel/linux/linux-5.10/drivers/phy/qualcomm/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
26 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
58 controllers on Qualcomm chips. This driver supports the high-speed
65 depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in
68 Support for the USB high-speed ULPI compliant phy on Qualcomm
76 Enable support for the USB high-speed SNPS Femto phy on Qualcomm
89 tristate "Qualcomm 28nm High-Speed PHY"
91 depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in
95 High-Speed PHY driver. This driver supports the Hi-Speed PHY which
100 tristate "Qualcomm USB Super-Speed PHY driver"
[all …]

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