Searched full:tcms (Results 1 – 7 of 7) sorted by relevance
89 * @tcm_is_double: flag to denote the larger unified TCMs in certain modes90 * @tcm_ecc_autoinit: flag to denote the auto-initialization of TCMs for ECC426 * from the internal TCMs. This function is used to release the resets on427 * applicable cores to allow loading into the TCMs. The .prepare() ops is432 * execute code, but combines the TCMs from both cores. The resets for both433 * cores need to be released to make this possible, as the TCMs are in general467 * of TCMs, so there is no need to perform the s/w memzero. This bit is in k3_r5_rproc_prepare()477 * Zero out both TCMs unconditionally (access from v8 Arm core is not in k3_r5_rproc_prepare()499 * The Single-CPU mode on applicable SoCs (eg: AM64x) combines the TCMs from742 /* handle R5-view addresses of TCMs */ in k3_r5_rproc_da_to_va()[all …]
526 /* clear TCMs */ in tcm_mem_map()
22 Core1's TCMs as well.102 caches. Each of the TCMs can be enabled or disabled independently and182 if omitted. Recommended to enable it for maximizing TCMs.
81 caches. Each of the TCMs can be enabled or disabled independently and158 if omitted. Recommended to enable it for maximizing TCMs.
354 * from the internal TCMs. This function is used to release the resets on355 * applicable cores to allow loading into the TCMs. The .prepare() ops is376 * Zero out both TCMs unconditionally (access from v8 Arm core is not in k3_r5_rproc_prepare()579 /* handle R5-view addresses of TCMs */ in k3_r5_rproc_da_to_va()586 /* handle SoC-view addresses of TCMs */ in k3_r5_rproc_da_to_va()636 * enable/disable each of the TCMs, control which TCM appears at the R5F core's1005 * TCMs are designed in general to support RAM-like backing in k3_r5_core_of_get_internal_memories()
45 TCMs in two separate banks, so for example an 8KiB ITCM is divided