| /kernel/linux/linux-5.10/include/asm-generic/ |
| D | tlb.h | 2 /* include/asm-generic/tlb.h
4 * Generic TLB shootdown code
35 * correct and efficient ordering of freeing pages and TLB invalidations.
40 * 2) TLB invalidate page
51 * Finish in particular will issue a (final) TLB invalidate and free
86 * tlb_flush_mmu_tlbonly() - does the TLB invalidate (and resets
89 * tlb_flush_mmu() - in addition to the above TLB invalidate, also frees
106 * flush the entire TLB irrespective of the range. For instance
125 * returns the smallest TLB entry size unmapped in this range.
138 * This might be useful if your architecture has size specific TLB
[all …]
|
| /kernel/linux/linux-6.6/include/asm-generic/ |
| D | tlb.h | 2 /* include/asm-generic/tlb.h
4 * Generic TLB shootdown code
35 * correct and efficient ordering of freeing pages and TLB invalidations.
40 * 2) TLB invalidate page
53 * Finish in particular will issue a (final) TLB invalidate and free
88 * tlb_flush_mmu_tlbonly() - does the TLB invalidate (and resets
91 * tlb_flush_mmu() - in addition to the above TLB invalidate, also frees
108 * flush the entire TLB irrespective of the range. For instance
127 * returns the smallest TLB entry size unmapped in this range.
140 * This might be useful if your architecture has size specific TLB
[all …]
|
| /kernel/linux/linux-6.6/mm/ |
| D | mmu_gather.c | 14 #include <asm/tlb.h>
18 static bool tlb_next_batch(struct mmu_gather *tlb) in tlb_next_batch() argument
23 if (tlb->delayed_rmap && tlb->active != &tlb->local) in tlb_next_batch()
26 batch = tlb->active; in tlb_next_batch()
28 tlb->active = batch->next; in tlb_next_batch()
32 if (tlb->batch_count == MAX_GATHER_BATCH_COUNT) in tlb_next_batch()
39 tlb->batch_count++; in tlb_next_batch()
44 tlb->active->next = batch; in tlb_next_batch()
45 tlb->active = batch; in tlb_next_batch()
64 * tlb_flush_rmaps - do pending rmap removals after we have flushed the TLB
[all …]
|
| /kernel/linux/linux-5.10/mm/ |
| D | mmu_gather.c | 12 #include <asm/tlb.h>
16 static bool tlb_next_batch(struct mmu_gather *tlb) in tlb_next_batch() argument
20 batch = tlb->active; in tlb_next_batch()
22 tlb->active = batch->next; in tlb_next_batch()
26 if (tlb->batch_count == MAX_GATHER_BATCH_COUNT) in tlb_next_batch()
33 tlb->batch_count++; in tlb_next_batch()
38 tlb->active->next = batch; in tlb_next_batch()
39 tlb->active = batch; in tlb_next_batch()
44 static void tlb_batch_pages_flush(struct mmu_gather *tlb) in tlb_batch_pages_flush() argument
48 for (batch = &tlb->local; batch && batch->nr; batch = batch->next) { in tlb_batch_pages_flush()
[all …]
|
| /kernel/linux/linux-5.10/arch/arm64/include/asm/ |
| D | tlb.h | 3 * Based on arch/arm/include/asm/tlb.h
20 static void tlb_flush(struct mmu_gather *tlb);
22 #include <asm-generic/tlb.h>
29 static inline int tlb_get_level(struct mmu_gather *tlb) in tlb_get_level() argument
32 if (tlb->freed_tables) in tlb_get_level()
35 if (tlb->cleared_ptes && !(tlb->cleared_pmds || in tlb_get_level()
36 tlb->cleared_puds || in tlb_get_level()
37 tlb->cleared_p4ds)) in tlb_get_level()
40 if (tlb->cleared_pmds && !(tlb->cleared_ptes || in tlb_get_level()
41 tlb->cleared_puds || in tlb_get_level()
[all …]
|
| /kernel/linux/linux-6.6/arch/arm64/include/asm/ |
| D | tlb.h | 3 * Based on arch/arm/include/asm/tlb.h
20 static void tlb_flush(struct mmu_gather *tlb);
22 #include <asm-generic/tlb.h>
29 static inline int tlb_get_level(struct mmu_gather *tlb) in tlb_get_level() argument
32 if (tlb->freed_tables) in tlb_get_level()
35 if (tlb->cleared_ptes && !(tlb->cleared_pmds || in tlb_get_level()
36 tlb->cleared_puds || in tlb_get_level()
37 tlb->cleared_p4ds)) in tlb_get_level()
40 if (tlb->cleared_pmds && !(tlb->cleared_ptes || in tlb_get_level()
41 tlb->cleared_puds || in tlb_get_level()
[all …]
|
| /kernel/linux/linux-5.10/arch/s390/include/asm/ |
| D | tlb.h | 6 * TLB flushing on s390 is complicated. The following requirement
14 * AND PURGE instruction that purges the TLB."
26 static inline void tlb_flush(struct mmu_gather *tlb);
27 static inline bool __tlb_remove_page_size(struct mmu_gather *tlb,
30 #define tlb_start_vma(tlb, vma) do { } while (0) argument
31 #define tlb_end_vma(tlb, vma) do { } while (0) argument
40 #include <asm-generic/tlb.h>
44 * tlb_ptep_clear_flush. In both flush modes the tlb for a page cache page
47 static inline bool __tlb_remove_page_size(struct mmu_gather *tlb, in __tlb_remove_page_size() argument
54 static inline void tlb_flush(struct mmu_gather *tlb) in tlb_flush() argument
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/ |
| D | tlb.json | 4 …TLB refills from any Instruction fetch. If there are multiple misses in the TLB that are resolved …
8 …TLB accesses that resulted in TLB refills. If there are multiple misses in the TLB that are resolv…
12 …TLB accesses caused by any memory load or store operation. Note that load or store instructions ca…
16 …ublicDescription": "Counts level 1 instruction TLB accesses, whether the access hits or misses in …
20 …ion": "Counts level 2 TLB refills caused by memory operations from both data and instruction fetch…
24 …"PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operation…
28 …TLB driven by a memory access. Note that partial translations that also cause a table walk are cou…
32 … L2 TLB driven by a memory access. Partial translations that also cause a table walk are counted. …
36 …TLB refills caused by memory read operations. If there are multiple misses in the TLB that are res…
40 …TLB refills caused by data side memory write operations. If there are multiple misses in the TLB t…
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/ |
| D | tlb.json | 4 …TLB refills from any Instruction fetch. If there are multiple misses in the TLB that are resolved …
8 …TLB accesses that resulted in TLB refills. If there are multiple misses in the TLB that are resolv…
12 …TLB accesses caused by any memory load or store operation. Note that load or store instructions ca…
16 …ublicDescription": "Counts level 1 instruction TLB accesses, whether the access hits or misses in …
20 …ion": "Counts level 2 TLB refills caused by memory operations from both data and instruction fetch…
24 …"PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operation…
28 …TLB driven by a memory access. Note that partial translations that also cause a table walk are cou…
32 … L2 TLB driven by a memory access. Partial translations that also cause a table walk are counted. …
36 …TLB refills caused by memory read operations. If there are multiple misses in the TLB that are res…
40 …TLB refills caused by data side memory write operations. If there are multiple misses in the TLB t…
[all …]
|
| /kernel/linux/linux-6.6/arch/s390/include/asm/ |
| D | tlb.h | 6 * TLB flushing on s390 is complicated. The following requirement
14 * AND PURGE instruction that purges the TLB."
26 static inline void tlb_flush(struct mmu_gather *tlb);
27 static inline bool __tlb_remove_page_size(struct mmu_gather *tlb,
38 #include <asm-generic/tlb.h>
42 * tlb_ptep_clear_flush. In both flush modes the tlb for a page cache page
48 static inline bool __tlb_remove_page_size(struct mmu_gather *tlb, in __tlb_remove_page_size() argument
56 static inline void tlb_flush(struct mmu_gather *tlb) in tlb_flush() argument
58 __tlb_flush_mm_lazy(tlb->mm); in tlb_flush()
63 * page table from the tlb.
[all …]
|
| /kernel/linux/linux-5.10/arch/loongarch/include/asm/ |
| D | tlb.h | 13 * TLB Invalidate Flush
26 * TLB R/W operations.
49 /* Invalid all tlb */
51 /* Invalid current tlb */
53 /* Invalid all global=1 lines in current tlb */
55 /* Invalid all global=0 lines in current tlb */
57 /* Invalid global=0 and matched asid lines in current tlb */
59 /* Invalid addr with global=0 and matched asid in current tlb */
61 /* Invalid addr with global=1 or matched asid in current tlb */
63 /* Invalid matched gid in guest tlb */
[all …]
|
| /kernel/linux/linux-6.6/arch/loongarch/include/asm/ |
| D | tlb.h | 13 * TLB Invalidate Flush
26 * TLB R/W operations.
49 /* Invalid all tlb */
51 /* Invalid current tlb */
53 /* Invalid all global=1 lines in current tlb */
55 /* Invalid all global=0 lines in current tlb */
57 /* Invalid global=0 and matched asid lines in current tlb */
59 /* Invalid addr with global=0 and matched asid in current tlb */
61 /* Invalid addr with global=1 or matched asid in current tlb */
63 /* Invalid matched gid in guest tlb */
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/powerpc/power8/ |
| D | translation.json | 5 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16G",
11 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16M",
17 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K",
23 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K",
29 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe…
35 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another …
41 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a data…
47 …"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the loc…
53 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without d…
59 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without confl…
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/powerpc/power8/ |
| D | translation.json | 5 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16G",
11 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16M",
17 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K",
23 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K",
29 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe…
35 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another …
41 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a data…
47 …"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the loc…
53 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without d…
59 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without confl…
[all …]
|
| /kernel/linux/linux-5.10/arch/mips/kvm/ |
| D | tlb.c | 6 * KVM/MIPS TLB handling, this file is part of the Linux host kernel so that
7 * TLB handlers run from KSEG0
26 #include <asm/tlb.h>
71 /* Structure defining an tlb entry data set. */
91 struct kvm_mips_tlb tlb; in kvm_mips_dump_guest_tlbs() local
98 tlb = vcpu->arch.guest_tlb[i]; in kvm_mips_dump_guest_tlbs()
99 kvm_info("TLB%c%3d Hi 0x%08lx ", in kvm_mips_dump_guest_tlbs()
100 (tlb.tlb_lo[0] | tlb.tlb_lo[1]) & ENTRYLO_V in kvm_mips_dump_guest_tlbs()
102 i, tlb.tlb_hi); in kvm_mips_dump_guest_tlbs()
104 (u64) mips3_tlbpfn_to_paddr(tlb.tlb_lo[0]), in kvm_mips_dump_guest_tlbs()
[all …]
|
| /kernel/linux/linux-5.10/arch/x86/include/asm/ |
| D | tlb.h | 5 #define tlb_start_vma(tlb, vma) do { } while (0) argument
6 #define tlb_end_vma(tlb, vma) do { } while (0) argument
7 #define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0) argument
10 static inline void tlb_flush(struct mmu_gather *tlb);
12 #include <asm-generic/tlb.h>
14 static inline void tlb_flush(struct mmu_gather *tlb) in tlb_flush() argument
17 unsigned int stride_shift = tlb_get_unmap_shift(tlb); in tlb_flush()
19 if (!tlb->fullmm && !tlb->need_flush_all) { in tlb_flush()
20 start = tlb->start; in tlb_flush()
21 end = tlb->end; in tlb_flush()
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/ |
| D | cache.json | 9 …ublicDescription": "L1 instruction TLB refill. This event counts any refill of the instruction L1 …
12 "BriefDescription": "L1 instruction TLB refill"
27 …"PublicDescription": "L1 data TLB refill. This event counts any refill of the data L1 TLB from the…
30 "BriefDescription": "L1 data TLB refill"
69 …blicDescription": "Level 1 data TLB access. This event counts any load or store operation which ac…
72 "BriefDescription": "Level 1 data TLB access."
75 …cription": "Level 1 instruction TLB access. This event counts any instruction fetch which accesses…
78 "BriefDescription": "Level 1 instruction TLB access"
99 …cDescription": "Attributable L2 data or unified TLB refill. This event counts on anyrefill of the …
102 "BriefDescription": "Attributable L2 data or unified TLB refill"
[all …]
|
| /kernel/linux/linux-6.6/arch/riscv/include/asm/ |
| D | tlb.h | 11 static void tlb_flush(struct mmu_gather *tlb);
14 #include <asm-generic/tlb.h>
16 static inline void tlb_flush(struct mmu_gather *tlb) in tlb_flush() argument
19 if (tlb->fullmm || tlb->need_flush_all || tlb->freed_tables) in tlb_flush()
20 flush_tlb_mm(tlb->mm); in tlb_flush()
22 flush_tlb_mm_range(tlb->mm, tlb->start, tlb->end, in tlb_flush()
23 tlb_get_unmap_size(tlb)); in tlb_flush()
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/skylakex/ |
| D | virtual-memory.json | 6 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal…
14 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).…
28 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
31 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can …
39 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
47 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
55 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
71 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal…
79 … "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
93 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/skylake/ |
| D | virtual-memory.json | 6 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal…
14 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).…
28 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
31 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can …
39 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
47 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
55 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
71 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal…
79 … "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
93 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| D | virtual-memory.json | 6 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal…
14 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).…
28 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
31 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can …
39 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
47 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
55 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
71 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal…
79 … "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
93 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| D | virtual-memory.json | 6 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).…
20 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
23 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can …
31 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
39 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
47 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
63 …ublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
77 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
80 …mand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can …
88 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
[all …]
|
| /kernel/linux/linux-6.6/arch/mips/kvm/ |
| D | tlb.c | 6 * KVM/MIPS TLB handling, this file is part of the Linux host kernel so that
7 * TLB handlers run from KSEG0
26 #include <asm/tlb.h>
92 * Sets the root GuestID to match the current guest GuestID, for TLB operation
93 * on the GPA->RPA mappings in the root TLB.
96 * possibly longer if TLB registers are modified.
121 /* Set root GuestID for root probe and write of guest TLB entry */ in kvm_vz_host_tlb_inv()
137 * We don't want to get reserved instruction exceptions for missing tlb in kvm_vz_host_tlb_inv()
153 * kvm_vz_guest_tlb_lookup() - Lookup a guest VZ TLB mapping.
155 * @gpa: Guest virtual address in a TLB mapped guest segment.
[all …]
|
| /kernel/linux/linux-6.6/arch/x86/include/asm/ |
| D | tlb.h | 6 static inline void tlb_flush(struct mmu_gather *tlb);
8 #include <asm-generic/tlb.h>
10 static inline void tlb_flush(struct mmu_gather *tlb) in tlb_flush() argument
13 unsigned int stride_shift = tlb_get_unmap_shift(tlb); in tlb_flush()
15 if (!tlb->fullmm && !tlb->need_flush_all) { in tlb_flush()
16 start = tlb->start; in tlb_flush()
17 end = tlb->end; in tlb_flush()
20 flush_tlb_mm_range(tlb->mm, start, end, stride_shift, tlb->freed_tables); in tlb_flush()
24 * While x86 architecture in general requires an IPI to perform TLB
29 * below 'ifdef CONFIG_MMU_GATHER_RCU_TABLE_FREE' in include/asm-generic/tlb.h
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/icelakex/ |
| D | virtual-memory.json | 6 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).…
20 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
23 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can …
31 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
39 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
47 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
63 …ublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
77 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
80 …mand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can …
88 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
[all …]
|