| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/thermal/ |
| D | exynos-thermal.txt | 1 * Exynos Thermal Management Unit (TMU)
6 "samsung,exynos3250-tmu"
7 "samsung,exynos4412-tmu"
8 "samsung,exynos4210-tmu"
9 "samsung,exynos5250-tmu"
10 "samsung,exynos5260-tmu"
11 "samsung,exynos5420-tmu" for TMU channel 0, 1 on Exynos5420
12 "samsung,exynos5420-tmu-ext-triminfo" for TMU channels 2, 3 and 4
14 "samsung,exynos5433-tmu"
15 "samsung,exynos7-tmu"
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| D | qoriq-thermal.yaml | 7 title: Thermal Monitoring Unit (TMU) on Freescale QorIQ SoCs
15 The version of the device is determined by the TMU IP Block Revision
22 - fsl,qoriq-tmu
23 - fsl,imx8mq-tmu
31 fsl,tmu-range:
38 fsl,tmu-calibration:
54 boolean, if present, the TMU registers are little endian. If absent,
68 - fsl,tmu-range
69 - fsl,tmu-calibration
76 tmu@f0000 {
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| D | imx8mm-thermal.yaml | 13 i.MX8MM has TMU IP to allow temperature measurement, there are
23 - fsl,imx8mm-tmu
24 - fsl,imx8mp-tmu
26 - const: fsl,imx8mn-tmu
27 - const: fsl,imx8mm-tmu
56 compatible = "fsl,imx8mm-tmu";
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/thermal/ |
| D | samsung,exynos-thermal.yaml | 7 title: Samsung Exynos SoC Thermal Management Unit (TMU)
13 For multi-instance tmu each instance should have an alias correctly numbered
19 - samsung,exynos3250-tmu
20 - samsung,exynos4412-tmu
21 - samsung,exynos4210-tmu
22 - samsung,exynos5250-tmu
23 - samsung,exynos5260-tmu
24 # For TMU channel 0, 1 on Exynos5420:
25 - samsung,exynos5420-tmu
26 # For TMU channels 2, 3 and 4 of Exynos5420:
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| D | qoriq-thermal.yaml | 7 title: Thermal Monitoring Unit (TMU) on Freescale QorIQ SoCs
15 The version of the device is determined by the TMU IP Block Revision
22 - fsl,qoriq-tmu
23 - fsl,imx8mq-tmu
31 fsl,tmu-range:
38 fsl,tmu-calibration:
54 boolean, if present, the TMU registers are little endian. If absent,
68 - fsl,tmu-range
69 - fsl,tmu-calibration
76 tmu@f0000 {
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| D | imx8mm-thermal.yaml | 13 i.MX8MM has TMU IP to allow temperature measurement, there are
23 - fsl,imx8mm-tmu
24 - fsl,imx8mp-tmu
26 - const: fsl,imx8mn-tmu
27 - const: fsl,imx8mm-tmu
63 compatible = "fsl,imx8mm-tmu";
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| /kernel/linux/linux-5.10/drivers/thermal/ |
| D | imx8mm_thermal.c | 20 #define TER 0x0 /* TMU enable */
22 #define TRITSR 0x20 /* TMU immediate temp */
64 struct imx8mm_tmu *tmu = sensor->priv; in imx8mm_tmu_get_temp() local
67 val = readl_relaxed(tmu->base + TRITSR) & TRITSR_TEMP0_VAL_MASK; in imx8mm_tmu_get_temp()
71 * ERR051272: TMU: Bit 31 of registers TMU_TSCR/TMU_TRITSR/TMU_TRATSR invalid in imx8mm_tmu_get_temp()
84 struct imx8mm_tmu *tmu = sensor->priv; in imx8mp_tmu_get_temp() local
88 val = readl_relaxed(tmu->base + TRITSR); in imx8mp_tmu_get_temp()
108 struct imx8mm_tmu *tmu = sensor->priv; in tmu_get_temp() local
110 return tmu->socdata->get_temp(data, temp); in tmu_get_temp()
117 static void imx8mm_tmu_enable(struct imx8mm_tmu *tmu, bool enable) in imx8mm_tmu_enable() argument
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| D | qoriq_thermal.c | 55 #define REGS_V2_TMSAR(n) (0x304 + 16 * (n)) /* TMU monitoring
93 * For TMU Rev1: in tmu_get_temp()
101 * For TMU Rev2: in tmu_get_temp()
178 len = of_property_count_u32_elems(np, "fsl,tmu-range"); in qoriq_tmu_calibration()
184 val = of_property_read_u32_array(np, "fsl,tmu-range", range, len); in qoriq_tmu_calibration()
194 calibration = of_get_property(np, "fsl,tmu-calibration", &len); in qoriq_tmu_calibration()
322 qoriq_tmu_init_device(data); /* TMU initialization */ in qoriq_tmu_probe()
324 ret = qoriq_tmu_calibration(dev, data); /* TMU calibration */ in qoriq_tmu_probe()
370 { .compatible = "fsl,qoriq-tmu", },
371 { .compatible = "fsl,imx8mq-tmu", },
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| /kernel/linux/linux-6.6/drivers/clocksource/ |
| D | sh_tmu.c | 3 * SuperH Timer Support - TMU
39 struct sh_tmu_device *tmu; member
89 switch (ch->tmu->model) { in sh_tmu_read()
91 return ioread8(ch->tmu->mapbase + 2); in sh_tmu_read()
93 return ioread8(ch->tmu->mapbase + 4); in sh_tmu_read()
111 switch (ch->tmu->model) { in sh_tmu_write()
113 return iowrite8(value, ch->tmu->mapbase + 2); in sh_tmu_write()
115 return iowrite8(value, ch->tmu->mapbase + 4); in sh_tmu_write()
132 raw_spin_lock_irqsave(&ch->tmu->lock, flags); in sh_tmu_start_stop_ch()
141 raw_spin_unlock_irqrestore(&ch->tmu->lock, flags); in sh_tmu_start_stop_ch()
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| /kernel/linux/linux-5.10/drivers/clocksource/ |
| D | sh_tmu.c | 3 * SuperH Timer Support - TMU
39 struct sh_tmu_device *tmu; member
89 switch (ch->tmu->model) { in sh_tmu_read()
91 return ioread8(ch->tmu->mapbase + 2); in sh_tmu_read()
93 return ioread8(ch->tmu->mapbase + 4); in sh_tmu_read()
111 switch (ch->tmu->model) { in sh_tmu_write()
113 return iowrite8(value, ch->tmu->mapbase + 2); in sh_tmu_write()
115 return iowrite8(value, ch->tmu->mapbase + 4); in sh_tmu_write()
132 raw_spin_lock_irqsave(&ch->tmu->lock, flags); in sh_tmu_start_stop_ch()
141 raw_spin_unlock_irqrestore(&ch->tmu->lock, flags); in sh_tmu_start_stop_ch()
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| /kernel/linux/linux-6.6/drivers/thermal/ |
| D | imx8mm_thermal.c | 21 #define TER 0x0 /* TMU enable */
23 #define TRITSR 0x20 /* TMU immediate temp */
24 /* TMU calibration data registers */
52 /* TMU OCOTP calibration data bitfields */
100 struct imx8mm_tmu *tmu = sensor->priv; in imx8mm_tmu_get_temp() local
103 val = readl_relaxed(tmu->base + TRITSR) & TRITSR_TEMP0_VAL_MASK; in imx8mm_tmu_get_temp()
107 * ERR051272: TMU: Bit 31 of registers TMU_TSCR/TMU_TRITSR/TMU_TRATSR invalid in imx8mm_tmu_get_temp()
120 struct imx8mm_tmu *tmu = sensor->priv; in imx8mp_tmu_get_temp() local
124 val = readl_relaxed(tmu->base + TRITSR); in imx8mp_tmu_get_temp()
144 struct imx8mm_tmu *tmu = sensor->priv; in tmu_get_temp() local
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/ |
| D | renesas,tmu.txt | 1 * Renesas R-Mobile/R-Car Timer Unit (TMU)
3 The TMU is a 32-bit timer/counter with configurable clock inputs and
7 are independent. The TMU hardware supports up to three channels.
12 - "renesas,tmu-r8a7740" for the r8a7740 TMU
13 - "renesas,tmu-r8a774a1" for the r8a774A1 TMU
14 - "renesas,tmu-r8a774b1" for the r8a774B1 TMU
15 - "renesas,tmu-r8a774c0" for the r8a774C0 TMU
16 - "renesas,tmu-r8a7778" for the r8a7778 TMU
17 - "renesas,tmu-r8a7779" for the r8a7779 TMU
18 - "renesas,tmu-r8a77970" for the r8a77970 TMU
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/timer/ |
| D | renesas,tmu.yaml | 4 $id: http://devicetree.org/schemas/timer/renesas,tmu.yaml#
7 title: Renesas R-Mobile/R-Car Timer Unit (TMU)
14 The TMU is a 32-bit timer/counter with configurable clock inputs and
18 are independent. The TMU hardware supports up to three channels.
24 - renesas,tmu-r8a7740 # R-Mobile A1
25 - renesas,tmu-r8a774a1 # RZ/G2M
26 - renesas,tmu-r8a774b1 # RZ/G2N
27 - renesas,tmu-r8a774c0 # RZ/G2E
28 - renesas,tmu-r8a774e1 # RZ/G2H
29 - renesas,tmu-r8a7778 # R-Car M1A
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| /kernel/linux/linux-6.6/drivers/thunderbolt/ |
| D | tmu.c | 3 * Thunderbolt Time Management Unit (TMU) support
73 sw->tmu.cap + TMU_RTR_CS_0, 1); in tb_switch_set_tmu_mode_params()
81 sw->tmu.cap + TMU_RTR_CS_0, 1); in tb_switch_set_tmu_mode_params()
86 sw->tmu.cap + TMU_RTR_CS_15, 1); in tb_switch_set_tmu_mode_params()
100 sw->tmu.cap + TMU_RTR_CS_15, 1); in tb_switch_set_tmu_mode_params()
108 sw->tmu.cap + TMU_RTR_CS_18, 1); in tb_switch_set_tmu_mode_params()
116 sw->tmu.cap + TMU_RTR_CS_18, 1); in tb_switch_set_tmu_mode_params()
128 sw->tmu.cap + TMU_RTR_CS_0, 1); in tb_switch_tmu_ucap_is_supported()
141 sw->tmu.cap + TMU_RTR_CS_3, 1); in tb_switch_tmu_rate_read()
155 sw->tmu.cap + TMU_RTR_CS_3, 1); in tb_switch_tmu_rate_write()
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| /kernel/linux/linux-5.10/drivers/thunderbolt/ |
| D | tmu.c | 3 * Thunderbolt Time Management Unit (TMU) support
18 switch (sw->tmu.rate) { in tb_switch_tmu_mode_name()
26 if (sw->tmu.unidirectional) in tb_switch_tmu_mode_name()
46 sw->tmu.cap + TMU_RTR_CS_0, 1); in tb_switch_tmu_ucap_supported()
59 sw->tmu.cap + TMU_RTR_CS_3, 1); in tb_switch_tmu_rate_read()
73 sw->tmu.cap + TMU_RTR_CS_3, 1); in tb_switch_tmu_rate_write()
81 sw->tmu.cap + TMU_RTR_CS_3, 1); in tb_switch_tmu_rate_write()
106 if (!port->sw->tmu.has_ucap) in tb_port_tmu_set_unidirectional()
137 sw->tmu.cap + TMU_RTR_CS_0, 1); in tb_switch_tmu_set_time_disruption()
147 sw->tmu.cap + TMU_RTR_CS_0, 1); in tb_switch_tmu_set_time_disruption()
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| /kernel/linux/linux-5.10/Documentation/driver-api/thermal/ |
| D | exynos_thermal.rst | 14 TMU controller Description:
46 TMU(Thermal Management Unit) in Exynos4/5 generates interrupt
64 TMU driver description:
74 TMU configuration data -----> TMU Driver <----> Exynos Core thermal wrapper
78 a) TMU configuration data:
79 This consist of TMU register offsets/bitfields
82 are used to configure the TMU.
83 b) TMU driver:
84 This component initialises the TMU controller and sets different
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| /kernel/linux/linux-6.6/Documentation/driver-api/thermal/ |
| D | exynos_thermal.rst | 14 TMU controller Description:
46 TMU(Thermal Management Unit) in Exynos4/5 generates interrupt
64 TMU driver description:
74 TMU configuration data -----> TMU Driver <----> Exynos Core thermal wrapper
78 a) TMU configuration data:
79 This consist of TMU register offsets/bitfields
82 are used to configure the TMU.
83 b) TMU driver:
84 This component initialises the TMU controller and sets different
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| /kernel/linux/linux-6.6/drivers/platform/x86/intel/ |
| D | bxtwc_tmu.c | 3 * Intel BXT Whiskey Cove PMIC TMU driver
7 * This driver adds TMU (Time Management Unit) support for Intel BXT platform.
8 * It enables the alarm wake-up functionality in the TMU unit of Whiskey Cove
38 /* Read TMU interrupt reg */ in bxt_wcove_tmu_irq_handler()
41 /* clear TMU irq */ in bxt_wcove_tmu_irq_handler()
74 /* Unmask TMU second level Wake & System alarm */ in bxt_wcove_tmu_probe()
87 /* Mask TMU interrupts */ in bxt_wcove_tmu_remove()
136 MODULE_DESCRIPTION("BXT Whiskey Cove TMU Driver");
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| /kernel/linux/linux-5.10/drivers/platform/x86/ |
| D | intel_bxtwc_tmu.c | 3 * Intel BXT Whiskey Cove PMIC TMU driver
7 * This driver adds TMU (Time Management Unit) support for Intel BXT platform.
8 * It enables the alarm wake-up functionality in the TMU unit of Whiskey Cove
38 /* Read TMU interrupt reg */ in bxt_wcove_tmu_irq_handler()
41 /* clear TMU irq */ in bxt_wcove_tmu_irq_handler()
84 /* Unmask TMU second level Wake & System alarm */ in bxt_wcove_tmu_probe()
97 /* Mask TMU interrupts */ in bxt_wcove_tmu_remove()
147 MODULE_DESCRIPTION("BXT Whiskey Cove TMU Driver");
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| /kernel/linux/linux-6.6/drivers/thermal/samsung/ |
| D | exynos_tmu.c | 3 * exynos_tmu.c - Samsung Exynos TMU (Thermal Management Unit)
139 * struct exynos_tmu_data : A structure to hold the private data of the TMU
141 * @id: identifier of the one instance of the TMU controller.
142 * @base: base address of the single instance of the TMU controller.
143 * @base_second: base address of the common registers of the TMU controller.
144 * @irq: irq number of the TMU controller.
150 * @sclk: pointer to the clock structure for accessing the tmu special clk.
162 * @regulator: pointer to the TMU regulator structure.
166 * @enabled: current status of TMU device
169 * @tmu_initialize: SoC specific TMU initialization method
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| D | Kconfig | 7 If you say yes here you get support for the TMU (Thermal Management
9 the TMU, reports temperature and handles cooling action if defined.
10 This driver uses the Exynos core thermal APIs and TMU configuration
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| /kernel/linux/linux-5.10/drivers/thermal/samsung/ |
| D | exynos_tmu.c | 3 * exynos_tmu.c - Samsung Exynos TMU (Thermal Management Unit)
140 * struct exynos_tmu_data : A structure to hold the private data of the TMU
142 * @id: identifier of the one instance of the TMU controller.
143 * @base: base address of the single instance of the TMU controller.
144 * @base_second: base address of the common registers of the TMU controller.
145 * @irq: irq number of the TMU controller.
151 * @sclk: pointer to the clock structure for accessing the tmu special clk.
163 * @regulator: pointer to the TMU regulator structure.
167 * @enabled: current status of TMU device
170 * @tmu_initialize: SoC specific TMU initialization method
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| D | Kconfig | 7 If you say yes here you get support for the TMU (Thermal Management
9 the TMU, reports temperature and handles cooling action if defined.
10 This driver uses the Exynos core thermal APIs and TMU configuration
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| /kernel/linux/linux-5.10/drivers/gpu/drm/vc4/ |
| D | vc4_validate_shaders.c | 31 * (reading it as a texture, uniform data, or direct-addressed TMU
157 int tmu) in record_texture_sample() argument
170 &validation_state->tmu_setup[tmu], in record_texture_sample()
177 validation_state->tmu_setup[tmu].p_offset[i] = ~0; in record_texture_sample()
193 int tmu = waddr > QPU_W_TMU0_B; in check_tmu_write() local
195 bool is_direct = submit && validation_state->tmu_write_count[tmu] == 0; in check_tmu_write()
203 DRM_DEBUG("direct TMU read used small immediate\n"); in check_tmu_write()
212 DRM_DEBUG("direct TMU load wasn't an add\n"); in check_tmu_write()
223 DRM_DEBUG("direct TMU load wasn't clamped\n"); in check_tmu_write()
229 DRM_DEBUG("direct TMU load wasn't clamped\n"); in check_tmu_write()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/vc4/ |
| D | vc4_validate_shaders.c | 31 * (reading it as a texture, uniform data, or direct-addressed TMU
157 int tmu) in record_texture_sample() argument
170 &validation_state->tmu_setup[tmu], in record_texture_sample()
177 validation_state->tmu_setup[tmu].p_offset[i] = ~0; in record_texture_sample()
193 int tmu = waddr > QPU_W_TMU0_B; in check_tmu_write() local
195 bool is_direct = submit && validation_state->tmu_write_count[tmu] == 0; in check_tmu_write()
203 DRM_DEBUG("direct TMU read used small immediate\n"); in check_tmu_write()
212 DRM_DEBUG("direct TMU load wasn't an add\n"); in check_tmu_write()
223 DRM_DEBUG("direct TMU load wasn't clamped\n"); in check_tmu_write()
229 DRM_DEBUG("direct TMU load wasn't clamped\n"); in check_tmu_write()
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