| /kernel/linux/linux-6.6/drivers/phy/marvell/ |
| D | phy-mvebu-a3700-utmi.c | 9 * Marvell A3700 UTMI PHY driver
21 /* Armada 3700 UTMI PHY registers */
62 * - The UTMI PHY wired to the USB3/USB2 controller (otg)
63 * - The UTMI PHY wired to the USB2 controller (host only)
88 struct mvebu_a3700_utmi *utmi = phy_get_drvdata(phy); in mvebu_a3700_utmi_phy_power_on() local
90 int usb32 = utmi->caps->usb32; in mvebu_a3700_utmi_phy_power_on()
98 reg = readl(utmi->regs + USB2_PHY_PLL_CTRL_REG0); in mvebu_a3700_utmi_phy_power_on()
102 writel(reg, utmi->regs + USB2_PHY_PLL_CTRL_REG0); in mvebu_a3700_utmi_phy_power_on()
105 regmap_update_bits(utmi->usb_misc, USB2_PHY_CTRL(usb32), in mvebu_a3700_utmi_phy_power_on()
111 reg = readl(utmi->regs + USB2_PHY_OTG_CTRL); in mvebu_a3700_utmi_phy_power_on()
[all …]
|
| D | phy-mvebu-cp110-utmi.c | 8 * Marvell CP110 UTMI PHY driver
24 /* CP110 UTMI register macro definetions */
167 struct mvebu_cp110_utmi *utmi = port->priv; in mvebu_cp110_utmi_phy_power_off() local
170 /* Power down UTMI PHY port */ in mvebu_cp110_utmi_phy_power_off()
171 regmap_clear_bits(utmi->syscon, SYSCON_UTMI_CFG_REG(port->id), in mvebu_cp110_utmi_phy_power_off()
175 int test = regmap_test_bits(utmi->syscon, in mvebu_cp110_utmi_phy_power_off()
178 /* skip PLL shutdown if there are active UTMI PHY ports */ in mvebu_cp110_utmi_phy_power_off()
183 /* PLL Power down if all UTMI PHYs are down */ in mvebu_cp110_utmi_phy_power_off()
184 regmap_clear_bits(utmi->syscon, SYSCON_USB_CFG_REG, USB_CFG_PLL_MASK); in mvebu_cp110_utmi_phy_power_off()
192 struct mvebu_cp110_utmi *utmi = port->priv; in mvebu_cp110_utmi_phy_power_on() local
[all …]
|
| D | Kconfig | 40 tristate "Marvell A3700 UTMI driver"
46 Enable this to support Marvell A3700 UTMI PHY driver.
71 tristate "Marvell CP110 UTMI driver"
76 Enable this to support Marvell CP110 UTMI PHY driver.
|
| /kernel/linux/linux-5.10/drivers/phy/marvell/ |
| D | phy-mvebu-a3700-utmi.c | 9 * Marvell A3700 UTMI PHY driver
21 /* Armada 3700 UTMI PHY registers */
62 * - The UTMI PHY wired to the USB3/USB2 controller (otg)
63 * - The UTMI PHY wired to the USB2 controller (host only)
88 struct mvebu_a3700_utmi *utmi = phy_get_drvdata(phy); in mvebu_a3700_utmi_phy_power_on() local
90 int usb32 = utmi->caps->usb32; in mvebu_a3700_utmi_phy_power_on()
98 reg = readl(utmi->regs + USB2_PHY_PLL_CTRL_REG0); in mvebu_a3700_utmi_phy_power_on()
102 writel(reg, utmi->regs + USB2_PHY_PLL_CTRL_REG0); in mvebu_a3700_utmi_phy_power_on()
105 regmap_update_bits(utmi->usb_misc, USB2_PHY_CTRL(usb32), in mvebu_a3700_utmi_phy_power_on()
111 reg = readl(utmi->regs + USB2_PHY_OTG_CTRL); in mvebu_a3700_utmi_phy_power_on()
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/at91/ |
| D | clk-utmi.c | 43 struct clk_utmi *utmi = to_clk_utmi(hw); in clk_utmi_prepare() local
52 * the utmi clock. in clk_utmi_prepare()
79 if (utmi->regmap_sfr) { in clk_utmi_prepare()
80 regmap_update_bits(utmi->regmap_sfr, AT91_SFR_UTMICKTRIM, in clk_utmi_prepare()
87 regmap_update_bits(utmi->regmap_pmc, AT91_CKGR_UCKR, uckr, uckr); in clk_utmi_prepare()
89 while (!clk_utmi_ready(utmi->regmap_pmc)) in clk_utmi_prepare()
97 struct clk_utmi *utmi = to_clk_utmi(hw); in clk_utmi_is_prepared() local
99 return clk_utmi_ready(utmi->regmap_pmc); in clk_utmi_is_prepared()
104 struct clk_utmi *utmi = to_clk_utmi(hw); in clk_utmi_unprepare() local
106 regmap_update_bits(utmi->regmap_pmc, AT91_CKGR_UCKR, in clk_utmi_unprepare()
[all …]
|
| /kernel/linux/linux-5.10/drivers/clk/at91/ |
| D | clk-utmi.c | 42 struct clk_utmi *utmi = to_clk_utmi(hw); in clk_utmi_prepare() local
51 * the utmi clock. in clk_utmi_prepare()
78 if (utmi->regmap_sfr) { in clk_utmi_prepare()
79 regmap_update_bits(utmi->regmap_sfr, AT91_SFR_UTMICKTRIM, in clk_utmi_prepare()
86 regmap_update_bits(utmi->regmap_pmc, AT91_CKGR_UCKR, uckr, uckr); in clk_utmi_prepare()
88 while (!clk_utmi_ready(utmi->regmap_pmc)) in clk_utmi_prepare()
96 struct clk_utmi *utmi = to_clk_utmi(hw); in clk_utmi_is_prepared() local
98 return clk_utmi_ready(utmi->regmap_pmc); in clk_utmi_is_prepared()
103 struct clk_utmi *utmi = to_clk_utmi(hw); in clk_utmi_unprepare() local
105 regmap_update_bits(utmi->regmap_pmc, AT91_CKGR_UCKR, in clk_utmi_unprepare()
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | marvell,armada-cp110-utmi-phy.yaml | 5 $id: http://devicetree.org/schemas/phy/marvell,armada-cp110-utmi-phy.yaml#
8 title: Marvell Armada CP110/CP115 UTMI PHY
15 Each of two exiting UTMI PHYs could be connected to either USB host or USB device
17 The USB device controller can only be connected to a single UTMI PHY port
19 UTMI PHY0 --------/
23 UTMI PHY1 --------\
28 const: marvell,cp110-utmi-phy
50 Each UTMI PHY port must be represented as a sub-node.
77 cp0_utmi: utmi@580000 {
78 compatible = "marvell,cp110-utmi-phy";
[all …]
|
| D | nvidia,tegra20-usb-phy.yaml | 50 - description: UTMI pads control registers clock
55 - description: UTMI timeout clock
56 - description: UTMI pads control registers clock
72 - const: utmi-pads
78 - const: utmi-pads
90 - description: UTMI pads reset
98 - const: utmi-pads
105 enum: [utmi, ulpi, hsic]
128 nvidia,has-utmi-pad-registers:
130 Indicates whether this controller contains the UTMI pad control
[all …]
|
| D | marvell,armada-3700-utmi-phy.yaml | 5 $id: http://devicetree.org/schemas/phy/marvell,armada-3700-utmi-phy.yaml#
8 title: Marvell Armada UTMI/UTMI+ PHY
17 a slightly different UTMI PHY.
22 - marvell,a3700-utmi-host-phy
23 - marvell,a3700-utmi-otg-phy
48 compatible = "marvell,a3700-utmi-host-phy";
|
| D | phy-stm32-usbphyc.yaml | 11 The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
12 switch. It controls PHY configuration and status, and the UTMI+ switch that
24 |_ UTMI switch_______| OTG controller
212 The value is used to select UTMI switch output.
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | nvidia,tegra20-usb-phy.txt | 13 - The register set of the PHY containing the UTMI pad control registers.
14 Present if-and-only-if phy_type == utmi.
15 - phy_type : Should be one of "utmi", "ulpi" or "hsic".
21 - timer: The timeout clock (clk_m). Present if phy_type == utmi.
22 - utmi-pads: The clock needed to access the UTMI pad control registers.
23 Present if phy_type == utmi.
32 - utmi-pads: The reset of the PHY containing the chip-wide UTMI pad control
38 Required PHY timing params for utmi phy, for all chips:
53 Required PHY timing params for utmi phy, only on Tegra30 and above:
70 - nvidia,has-utmi-pad-registers : boolean indicates whether this controller
[all …]
|
| D | phy-mvebu-utmi.txt | 1 MVEBU A3700 UTMI PHY
4 USB2 UTMI+ PHY controllers can be found on the following Marvell MVEBU SoCs:
10 different UTMI PHY.
15 * "marvell,a3700-utmi-host-phy" for the PHY connected to
17 * "marvell,a3700-utmi-otg-phy" for the PHY connected to
29 compatible = "marvell,armada-3700-utmi-host-phy";
|
| D | phy-stm32-usbphyc.txt | 3 The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
4 switch. It controls PHY configuration and status, and the UTMI+ switch that
16 |_ UTMI switch_______| OTG controller
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mfd/ |
| D | omap-usb-host.txt | 43 * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
44 * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
45 * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
46 * "utmi_p1_gfclk" - Port 1 UTMI clock mux.
47 * "utmi_p2_gfclk" - Port 2 UTMI clock mux.
48 * "usb_host_hs_utmi_p1_clk" - Port 1 UTMI clock gate.
49 * "usb_host_hs_utmi_p2_clk" - Port 2 UTMI clock gate.
50 * "usb_host_hs_utmi_p3_clk" - Port 3 UTMI clock gate.
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mfd/ |
| D | omap-usb-host.txt | 43 * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
44 * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
45 * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
46 * "utmi_p1_gfclk" - Port 1 UTMI clock mux.
47 * "utmi_p2_gfclk" - Port 2 UTMI clock mux.
48 * "usb_host_hs_utmi_p1_clk" - Port 1 UTMI clock gate.
49 * "usb_host_hs_utmi_p2_clk" - Port 2 UTMI clock gate.
50 * "usb_host_hs_utmi_p3_clk" - Port 3 UTMI clock gate.
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/usb/ |
| D | usb.yaml | 36 UTMI+ PHY with an 8- or 16-bit interface if UTMI+ is selected, UTMI+ low
42 enum: [utmi, utmi_wide, ulpi, serial, hsic]
|
| D | atmel-usb.txt | 37 - clocks: Should reference the peripheral and the UTMI clocks
40 "usb_clk" for the UTMI clock
44 "utmi", or "hsic".
50 clocks = <&utmi>, <&uhphs_clk>;
122 clocks = <&utmi>, <&udphs_clk>;
|
| D | omap-usb.txt | 13 specifying ULPI and UTMI respectively.
55 - utmi-mode : controls the source of UTMI/PIPE status for VBUS and OTG ID.
77 utmi-mode = <2>;
|
| D | hisilicon,histb-xhci.txt | 13 "utmi": for utmi clock
40 clock-names = "bus", "utmi", "pipe", "suspend";
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/ |
| D | omap-usb.txt | 13 specifying ULPI and UTMI respectively.
55 - utmi-mode : controls the source of UTMI/PIPE status for VBUS and OTG ID.
77 utmi-mode = <2>;
|
| D | hisilicon,histb-xhci.txt | 13 "utmi": for utmi clock
40 clock-names = "bus", "utmi", "pipe", "suspend";
|
| D | atmel-usb.txt | 37 - clocks: Should reference the peripheral and the UTMI clocks
40 "usb_clk" for the UTMI clock
46 clocks = <&utmi>, <&uhphs_clk>;
115 clocks = <&utmi>, <&udphs_clk>;
|
| D | generic.txt | 16 a UTMI+ PHY with an 8- or 16-bit interface if UTMI+ is
17 selected. Valid arguments are "utmi" and "utmi_wide".
|
| /kernel/linux/linux-6.6/drivers/media/usb/dvb-usb-v2/ |
| D | rtl28xxu.h | 197 #define USB_VDRCTRL 0x2F10 /* UTMI vendor signal control */
198 #define USB_VSTAIN 0x2F14 /* UTMI vendor signal status in */
199 #define USB_VLOADM 0x2F18 /* UTMI load vendor signal status in */
200 #define USB_VSTAOUT 0x2F1C /* UTMI vendor signal status out */
201 #define USB_UTMI_TST 0x2F80 /* UTMI test */
202 #define USB_UTMI_STATUS 0x2F84 /* UTMI status */
|
| /kernel/linux/linux-5.10/drivers/media/usb/dvb-usb-v2/ |
| D | rtl28xxu.h | 197 #define USB_VDRCTRL 0x2F10 /* UTMI vendor signal control */
198 #define USB_VSTAIN 0x2F14 /* UTMI vendor signal status in */
199 #define USB_VLOADM 0x2F18 /* UTMI load vendor signal status in */
200 #define USB_VSTAOUT 0x2F1C /* UTMI vendor signal status out */
201 #define USB_UTMI_TST 0x2F80 /* UTMI test */
202 #define USB_UTMI_STATUS 0x2F84 /* UTMI status */
|