| /kernel/linux/linux-6.6/drivers/staging/media/sunxi/sun6i-isp/ |
| D | sun6i_isp_reg.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2021-2022 Bootlin
20 #define SUN6I_ISP_FE_CFG_EN BIT(0)
21 #define SUN6I_ISP_FE_CFG_SRC0_MODE(v) (((v) << 8) & GENMASK(9, 8)) argument
22 #define SUN6I_ISP_FE_CFG_SRC1_MODE(v) (((v) << 16) & GENMASK(17, 16)) argument
25 #define SUN6I_ISP_FE_CTRL_SCAP_EN BIT(0)
26 #define SUN6I_ISP_FE_CTRL_VCAP_EN BIT(1)
27 #define SUN6I_ISP_FE_CTRL_PARA_READY BIT(2)
28 #define SUN6I_ISP_FE_CTRL_LUT_UPDATE BIT(3)
29 #define SUN6I_ISP_FE_CTRL_LENS_UPDATE BIT(4)
[all …]
|
| /kernel/linux/linux-5.10/drivers/mtd/nand/raw/ |
| D | nand_ids.c | 1 // SPDX-License-Identifier: GPL-2.0-only
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
41 {"TC58NVG5D2 32G 3.3V 8-bit",
44 {"TC58NVG6D2 64G 3.3V 8-bit",
47 {"SDTNRGAMA 64G 3.3V 8-bit",
50 {"H27UCG8T2ATR-BC 64G 3.3V 8-bit",
54 {"TH58NVG2S3HBAI4 4G 3.3V 8-bit",
[all …]
|
| /kernel/linux/linux-6.6/drivers/mtd/nand/raw/ |
| D | nand_ids.c | 1 // SPDX-License-Identifier: GPL-2.0-only
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
41 {"TC58NVG5D2 32G 3.3V 8-bit",
44 {"TC58NVG6D2 64G 3.3V 8-bit",
47 {"SDTNQGAMA 64G 3.3V 8-bit",
50 {"SDTNRGAMA 64G 3.3V 8-bit",
53 {"H27UCG8T2ATR-BC 64G 3.3V 8-bit",
[all …]
|
| /kernel/linux/linux-6.6/drivers/staging/media/sunxi/cedrus/ |
| D | cedrus_regs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (c) 2013-2016 Jens Kuske <jenskuske@gmail.com>
6 * Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com>
13 #define SHIFT_AND_MASK_BITS(v, h, l) \ argument
14 (((unsigned long)(v) << (l)) & GENMASK(h, l))
18 * * VLD : Variable-Length Decoder
38 #define VE_MODE_PIC_WIDTH_IS_4096 BIT(22)
39 #define VE_MODE_PIC_WIDTH_MORE_2048 BIT(21)
96 #define VE_DEC_MPEG_MP12HDR_F_CODE_SHIFT(x, y) (24 - 4 * (y) - 8 * (x))
104 #define VE_DEC_MPEG_MP12HDR_TOP_FIELD_FIRST(v) \ argument
[all …]
|
| /kernel/linux/linux-5.10/sound/soc/fsl/ |
| D | fsl_micfil.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
35 /* MICFIL Control Register 1 -- REG_MICFILL_CTRL1 0x00 */
37 #define MICFIL_CTRL1_MDIS_MASK BIT(MICFIL_CTRL1_MDIS_SHIFT)
38 #define MICFIL_CTRL1_MDIS BIT(MICFIL_CTRL1_MDIS_SHIFT)
40 #define MICFIL_CTRL1_DOZEN_MASK BIT(MICFIL_CTRL1_DOZEN_SHIFT)
41 #define MICFIL_CTRL1_DOZEN BIT(MICFIL_CTRL1_DOZEN_SHIFT)
43 #define MICFIL_CTRL1_PDMIEN_MASK BIT(MICFIL_CTRL1_PDMIEN_SHIFT)
44 #define MICFIL_CTRL1_PDMIEN BIT(MICFIL_CTRL1_PDMIEN_SHIFT)
46 #define MICFIL_CTRL1_DBG_MASK BIT(MICFIL_CTRL1_DBG_SHIFT)
47 #define MICFIL_CTRL1_DBG BIT(MICFIL_CTRL1_DBG_SHIFT)
[all …]
|
| D | fsl_easrc.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/platform_data/dma-imx.h>
88 #define EASRC_CC_EN_MASK BIT(EASRC_CC_EN_SHIFT)
89 #define EASRC_CC_EN BIT(EASRC_CC_EN_SHIFT)
91 #define EASRC_CC_STOP_MASK BIT(EASRC_CC_STOP_SHIFT)
92 #define EASRC_CC_STOP BIT(EASRC_CC_STOP_SHIFT)
94 #define EASRC_CC_FWMDE_MASK BIT(EASRC_CC_FWMDE_SHIFT)
95 #define EASRC_CC_FWMDE BIT(EASRC_CC_FWMDE_SHIFT)
98 #define EASRC_CC_FIFO_WTMK_MASK ((BIT(EASRC_CC_FIFO_WTMK_WIDTH) - 1) \
100 #define EASRC_CC_FIFO_WTMK(v) (((v) << EASRC_CC_FIFO_WTMK_SHIFT) \ argument
[all …]
|
| /kernel/linux/linux-5.10/drivers/staging/media/sunxi/cedrus/ |
| D | cedrus_regs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (c) 2013-2016 Jens Kuske <jenskuske@gmail.com>
6 * Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com>
13 #define SHIFT_AND_MASK_BITS(v, h, l) \ argument
14 (((unsigned long)(v) << (l)) & GENMASK(h, l))
18 * * VLD : Variable-Length Decoder
38 #define VE_MODE_PIC_WIDTH_IS_4096 BIT(22)
39 #define VE_MODE_PIC_WIDTH_MORE_2048 BIT(21)
96 #define VE_DEC_MPEG_MP12HDR_F_CODE_SHIFT(x, y) (24 - 4 * (y) - 8 * (x))
104 #define VE_DEC_MPEG_MP12HDR_TOP_FIELD_FIRST(v) \ argument
[all …]
|
| /kernel/linux/linux-6.6/sound/soc/fsl/ |
| D | fsl_easrc.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/dma/imx-dma.h>
88 #define EASRC_CC_EN_MASK BIT(EASRC_CC_EN_SHIFT)
89 #define EASRC_CC_EN BIT(EASRC_CC_EN_SHIFT)
91 #define EASRC_CC_STOP_MASK BIT(EASRC_CC_STOP_SHIFT)
92 #define EASRC_CC_STOP BIT(EASRC_CC_STOP_SHIFT)
94 #define EASRC_CC_FWMDE_MASK BIT(EASRC_CC_FWMDE_SHIFT)
95 #define EASRC_CC_FWMDE BIT(EASRC_CC_FWMDE_SHIFT)
98 #define EASRC_CC_FIFO_WTMK_MASK ((BIT(EASRC_CC_FIFO_WTMK_WIDTH) - 1) \
100 #define EASRC_CC_FIFO_WTMK(v) (((v) << EASRC_CC_FIFO_WTMK_SHIFT) \ argument
[all …]
|
| /kernel/linux/linux-5.10/drivers/staging/media/hantro/ |
| D | rk3399_vpu_hw_mpeg2_dec.c | 1 // SPDX-License-Identifier: GPL-2.0
10 #include <media/v4l2-mem2mem.h>
23 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
25 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
26 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
27 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
28 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
30 #define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) argument
31 #define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) argument
33 #define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17)) argument
[all …]
|
| D | hantro_g1_mpeg2_dec.c | 1 // SPDX-License-Identifier: GPL-2.0
10 #include <media/v4l2-mem2mem.h>
23 #define G1_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
25 #define G1_REG_DEC_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24)) argument
26 #define G1_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(23) : 0) argument
27 #define G1_REG_DEC_STRSWAP32_E(v) ((v) ? BIT(22) : 0) argument
28 #define G1_REG_DEC_STRENDIAN_E(v) ((v) ? BIT(21) : 0) argument
29 #define G1_REG_DEC_INSWAP32_E(v) ((v) ? BIT(20) : 0) argument
30 #define G1_REG_DEC_OUTSWAP32_E(v) ((v) ? BIT(19) : 0) argument
31 #define G1_REG_DEC_DATA_DISC_E(v) ((v) ? BIT(18) : 0) argument
[all …]
|
| /kernel/linux/linux-6.6/drivers/media/platform/verisilicon/ |
| D | rockchip_vpu2_hw_mpeg2_dec.c | 1 // SPDX-License-Identifier: GPL-2.0
10 #include <media/v4l2-mem2mem.h>
23 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
25 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
26 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
27 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
28 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
30 #define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) argument
31 #define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) argument
33 #define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17)) argument
[all …]
|
| D | hantro_g1_mpeg2_dec.c | 1 // SPDX-License-Identifier: GPL-2.0
10 #include <media/v4l2-mem2mem.h>
25 #define G1_REG_DEC_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24)) argument
26 #define G1_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(23) : 0) argument
27 #define G1_REG_DEC_STRSWAP32_E(v) ((v) ? BIT(22) : 0) argument
28 #define G1_REG_DEC_STRENDIAN_E(v) ((v) ? BIT(21) : 0) argument
29 #define G1_REG_DEC_INSWAP32_E(v) ((v) ? BIT(20) : 0) argument
30 #define G1_REG_DEC_OUTSWAP32_E(v) ((v) ? BIT(19) : 0) argument
31 #define G1_REG_DEC_DATA_DISC_E(v) ((v) ? BIT(18) : 0) argument
32 #define G1_REG_DEC_LATENCY(v) (((v) << 11) & GENMASK(16, 11)) argument
[all …]
|
| D | rockchip_vpu2_hw_h264_dec.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Hertz Wong <hertz.wong@rock-chips.com>
7 * Herman Chen <herman.chen@rock-chips.com>
16 #include <media/v4l2-mem2mem.h>
28 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
30 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
31 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
32 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
33 #define VDPU_REG_PIC_FIXED_QUANT(v) ((v) ? BIT(7) : 0) argument
34 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
[all …]
|
| /kernel/linux/linux-5.10/drivers/iio/adc/ |
| D | stm32-dfsdm.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
15 * STM32 DFSDM - global register map
18 * --------------------------------------------------------
20 * --------------------------------------------------------
22 * --------------------------------------------------------
24 * --------------------------------------------------------
26 * --------------------------------------------------------
28 * --------------------------------------------------------
30 * --------------------------------------------------------
[all …]
|
| /kernel/linux/linux-6.6/drivers/iio/adc/ |
| D | stm32-dfsdm.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
15 * STM32 DFSDM - global register map
18 * ----------------------------------------------------------
20 * ----------------------------------------------------------
22 * ----------------------------------------------------------
24 * ----------------------------------------------------------
26 * ----------------------------------------------------------
28 * ----------------------------------------------------------
30 * ----------------------------------------------------------
[all …]
|
| /kernel/linux/linux-6.6/drivers/net/ethernet/altera/ |
| D | altera_msgdmahw.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
17 u32 burst_seq_num; /* bit 31:24 write burst
18 * bit 23:16 read burst
19 * bit 15:0 sequence number
21 u32 stride; /* bit 31:16 write stride
22 * bit 15:0 read stride
29 /* mSGDMA descriptor control field bit definitions
32 #define MSGDMA_DESC_CTL_GEN_SOP BIT(8)
33 #define MSGDMA_DESC_CTL_GEN_EOP BIT(9)
34 #define MSGDMA_DESC_CTL_PARK_READS BIT(10)
[all …]
|
| D | altera_tse.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Altera Triple-Speed Ethernet MAC driver
3 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved
53 #define GET_BIT_VALUE(v, bit) (((v) >> (bit)) & 0x1) argument
55 /* MAC Command_Config Register Bit Definitions
57 #define MAC_CMDCFG_TX_ENA BIT(0)
58 #define MAC_CMDCFG_RX_ENA BIT(1)
59 #define MAC_CMDCFG_XON_GEN BIT(2)
60 #define MAC_CMDCFG_ETH_SPEED BIT(3)
61 #define MAC_CMDCFG_PROMIS_EN BIT(4)
[all …]
|
| /kernel/linux/linux-5.10/drivers/net/ethernet/altera/ |
| D | altera_msgdmahw.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
17 u32 burst_seq_num; /* bit 31:24 write burst
18 * bit 23:16 read burst
19 * bit 15:0 sequence number
21 u32 stride; /* bit 31:16 write stride
22 * bit 15:0 read stride
29 /* mSGDMA descriptor control field bit definitions
32 #define MSGDMA_DESC_CTL_GEN_SOP BIT(8)
33 #define MSGDMA_DESC_CTL_GEN_EOP BIT(9)
34 #define MSGDMA_DESC_CTL_PARK_READS BIT(10)
[all …]
|
| D | altera_tse.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Altera Triple-Speed Ethernet MAC driver
3 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved
52 #define GET_BIT_VALUE(v, bit) (((v) >> (bit)) & 0x1) argument
54 /* MAC Command_Config Register Bit Definitions
56 #define MAC_CMDCFG_TX_ENA BIT(0)
57 #define MAC_CMDCFG_RX_ENA BIT(1)
58 #define MAC_CMDCFG_XON_GEN BIT(2)
59 #define MAC_CMDCFG_ETH_SPEED BIT(3)
60 #define MAC_CMDCFG_PROMIS_EN BIT(4)
[all …]
|
| /kernel/linux/linux-6.6/drivers/media/platform/sunxi/sun6i-csi/ |
| D | sun6i_csi_reg.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (c) 2011-2018 Magewell Electronics Co., Ltd. (Nanjing)
5 * Copyright 2021-2022 Bootlin
17 #define SUN6I_CSI_EN_VER_EN BIT(30)
18 #define SUN6I_CSI_EN_PTN_CYCLE(v) (((v) << 16) & GENMASK(23, 16)) argument
19 #define SUN6I_CSI_EN_SRAM_PWDN BIT(8)
20 #define SUN6I_CSI_EN_PTN_START BIT(4)
21 #define SUN6I_CSI_EN_CLK_CNT_SPL_VSYNC BIT(3)
22 #define SUN6I_CSI_EN_CLK_CNT_EN BIT(2)
23 #define SUN6I_CSI_EN_PTN_GEN_EN BIT(1)
[all …]
|
| /kernel/linux/linux-5.10/lib/ |
| D | atomic64_test.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
20 #define TEST(bit, op, c_op, val) \ argument
22 atomic##bit##_set(&v, v0); \
24 atomic##bit##_##op(val, &v); \
26 WARN(atomic##bit##_read(&v) != r, "%Lx != %Lx\n", \
27 (unsigned long long)atomic##bit##_read(&v), \
33 * @test should be a macro accepting parameters (bit, op, ...)
36 #define FAMILY_TEST(test, bit, op, args...) \ argument
38 test(bit, op, ##args); \
39 test(bit, op##_acquire, ##args); \
[all …]
|
| /kernel/linux/linux-6.6/lib/ |
| D | atomic64_test.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
20 #define TEST(bit, op, c_op, val) \ argument
22 atomic##bit##_set(&v, v0); \
24 atomic##bit##_##op(val, &v); \
26 WARN(atomic##bit##_read(&v) != r, "%Lx != %Lx\n", \
27 (unsigned long long)atomic##bit##_read(&v), \
33 * @test should be a macro accepting parameters (bit, op, ...)
36 #define FAMILY_TEST(test, bit, op, args...) \ argument
38 test(bit, op, ##args); \
39 test(bit, op##_acquire, ##args); \
[all …]
|
| /kernel/linux/linux-5.10/sound/soc/sunxi/ |
| D | sun4i-spdif.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
29 #define SUN4I_SPDIF_CTL_MCLKDIV(v) ((v) << 4) /* v even */ argument
30 #define SUN4I_SPDIF_CTL_MCLKOUTEN BIT(2)
31 #define SUN4I_SPDIF_CTL_GEN BIT(1)
32 #define SUN4I_SPDIF_CTL_RESET BIT(0)
35 #define SUN4I_SPDIF_TXCFG_SINGLEMOD BIT(31)
36 #define SUN4I_SPDIF_TXCFG_ASS BIT(17)
37 #define SUN4I_SPDIF_TXCFG_NONAUDIO BIT(16)
38 #define SUN4I_SPDIF_TXCFG_TXRATIO(v) ((v) << 4) argument
44 #define SUN4I_SPDIF_TXCFG_CHSTMODE BIT(1)
[all …]
|
| /kernel/linux/linux-6.6/drivers/media/platform/sunxi/sun8i-di/ |
| D | sun8i-di.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include <media/v4l2-device.h>
12 #include <media/v4l2-mem2mem.h>
13 #include <media/videobuf2-v4l2.h>
14 #include <media/videobuf2-dma-contig.h>
18 #define DEINTERLACE_NAME "sun8i-di"
21 #define DEINTERLACE_MOD_ENABLE_EN BIT(0)
24 #define DEINTERLACE_FRM_CTRL_REG_READY BIT(0)
25 #define DEINTERLACE_FRM_CTRL_WB_EN BIT(2)
26 #define DEINTERLACE_FRM_CTRL_OUT_CTRL BIT(11)
[all …]
|
| /kernel/linux/linux-5.10/drivers/media/platform/sunxi/sun8i-di/ |
| D | sun8i-di.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include <media/v4l2-device.h>
12 #include <media/v4l2-mem2mem.h>
13 #include <media/videobuf2-v4l2.h>
14 #include <media/videobuf2-dma-contig.h>
18 #define DEINTERLACE_NAME "sun8i-di"
21 #define DEINTERLACE_MOD_ENABLE_EN BIT(0)
24 #define DEINTERLACE_FRM_CTRL_REG_READY BIT(0)
25 #define DEINTERLACE_FRM_CTRL_WB_EN BIT(2)
26 #define DEINTERLACE_FRM_CTRL_OUT_CTRL BIT(11)
[all …]
|