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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/inc/
Dreg_helper.h34 * eg. aud110->base.ctx
37 * eg. aud110->regs->reg
67 #define REG_SET_2(reg, init_value, f1, v1, f2, v2) \ argument
69 FN(reg, f1), v1,\
72 #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \ argument
74 FN(reg, f1), v1,\
78 #define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \ argument
80 FN(reg, f1), v1,\
85 #define REG_SET_5(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ argument
88 FN(reg, f1), v1,\
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/inc/
Dreg_helper.h34 * eg. aud110->base.ctx
37 * eg. aud110->regs->reg
67 #define REG_SET_2(reg, init_value, f1, v1, f2, v2) \ argument
69 FN(reg, f1), v1,\
72 #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \ argument
74 FN(reg, f1), v1,\
78 #define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \ argument
80 FN(reg, f1), v1,\
85 #define REG_SET_5(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ argument
88 FN(reg, f1), v1,\
[all …]
/kernel/linux/linux-5.10/arch/powerpc/crypto/
Dcrc32-vpmsum_core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 * 32 bits of 0s to the end - this matches what a CRC does. We just
28 #include <asm/ppc-opcode.h>
66 std r31,-8(r1)
67 std r30,-16(r1)
68 std r29,-24(r1)
69 std r28,-32(r1)
70 std r27,-40(r1)
71 std r26,-48(r1)
72 std r25,-56(r1)
[all …]
/kernel/linux/linux-6.6/arch/powerpc/crypto/
Dcrc32-vpmsum_core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 * 32 bits of 0s to the end - this matches what a CRC does. We just
28 #include <asm/ppc-opcode.h>
66 std r31,-8(r1)
67 std r30,-16(r1)
68 std r29,-24(r1)
69 std r28,-32(r1)
70 std r27,-40(r1)
71 std r26,-48(r1)
72 std r25,-56(r1)
[all …]
/kernel/linux/linux-6.6/arch/arm64/crypto/
Dsm4-neon-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * https://tools.ietf.org/id/draft-ribose-cfrg-sm4-10.html
35 ld1 {v16.16b-v19.16b}, [x5], #64; \
36 ld1 {v20.16b-v23.16b}, [x5], #64; \
37 ld1 {v24.16b-v27.16b}, [x5], #64; \
38 ld1 {v28.16b-v31.16b}, [x5];
103 /* sbox, non-linear part */ \
105 tbl RTMP0.16b, {v16.16b-v19.16b}, RX0.16b; \
107 tbx RTMP0.16b, {v20.16b-v23.16b}, RX0.16b; \
109 tbx RTMP0.16b, {v24.16b-v27.16b}, RX0.16b; \
[all …]
Daes-neonbs-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
10 * 'Faster and Timing-Attack Resistant AES-GCM' by Emilia Kaesper and
14 * for 32-bit ARM written by Andy Polyakov <appro@openssl.org>
216 ldp q18, q19, [bskey, #-96]
217 ldp q20, q21, [bskey, #-64]
218 ldp q22, q23, [bskey, #-32]
222 ldp q16, q17, [bskey, #-128]!
406 cmtst v1.16b, v7.16b, v9.16b
411 cmtst v6.16b, v7.16b, v14.16b
414 not v1.16b, v1.16b
[all …]
Daes-modes.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm64/crypto/aes-modes.S - chaining mode wrappers for AES
5 * Copyright (C) 2013 - 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
8 /* included by aes-ce.S and aes-neon.S */
26 encrypt_block4x v0, v1, v2, v3, w3, x2, x8, w7
31 decrypt_block4x v0, v1, v2, v3, w3, x2, x8, w7
37 encrypt_block5x v0, v1, v2, v3, v4, w3, x2, x8, w7
42 decrypt_block5x v0, v1, v2, v3, v4, w3, x2, x8, w7
62 ld1 {v0.16b-v3.16b}, [x1], #64 /* get 4 pt blocks */
66 st1 {v0.16b-v3.16b}, [x0], #64
[all …]
Dsm4-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * https://tools.ietf.org/id/draft-ribose-cfrg-sm4-10.html
13 #include "sm4-ce-asm.h"
15 .arch armv8-a+crypto
45 * x0: 128-bit key
53 ld1 {v1.16b}, [x3];
55 ld1 {v24.16b-v27.16b}, [x4], #64;
56 ld1 {v28.16b-v31.16b}, [x4];
59 eor v0.16b, v0.16b, v1.16b;
62 sm4ekey v1.4s, v0.4s, v25.4s;
[all …]
Dchacha-neon-core.S4 * Copyright (C) 2016-2018 Linaro, Ltd. <ard.biesheuvel@linaro.org>
11 * ChaCha20 256-bit cipher algorithm, RFC7539, x64 SSSE3 functions
29 * chacha_permute - permute one block
31 * Permute one 64-byte block where the state matrix is stored in the four NEON
32 * registers v0-v3. It performs matrix operations on four words in parallel,
46 add v0.4s, v0.4s, v1.4s
52 eor v4.16b, v1.16b, v2.16b
53 shl v1.4s, v4.4s, #12
54 sri v1.4s, v4.4s, #20
57 add v0.4s, v0.4s, v1.4s
[all …]
Dsha3-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha3-ce-core.S - core SHA-3 transform using v8.2 Crypto Extensions
46 ld1 { v0.1d- v3.1d}, [x0]
47 ld1 { v4.1d- v7.1d}, [x8], #32
48 ld1 { v8.1d-v11.1d}, [x8], #32
49 ld1 {v12.1d-v15.1d}, [x8], #32
50 ld1 {v16.1d-v19.1d}, [x8], #32
51 ld1 {v20.1d-v23.1d}, [x8], #32
59 ld1 {v25.8b-v28.8b}, [x1], #32
60 ld1 {v29.8b-v31.8b}, [x1], #24
[all …]
Dcrct10dif-ce-core.S2 // Accelerated CRC-T10DIF using arm64 NEON and Crypto Extensions instructions
14 // Implement fast CRC-T10DIF computation with SSE and PCLMULQDQ instructions
62 // /white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf
69 .arch armv8-a+crypto
276 CPU_LE( rev64 v1.16b, v1.16b )
281 CPU_LE( rev64 v6.16b, v6.16b )
284 CPU_LE( ext v1.16b, v1.16b, v1.16b, #8 )
289 CPU_LE( ext v6.16b, v6.16b, v6.16b, #8 )
305 // While >= 128 data bytes remain (not counting v0-v7), fold the 128
306 // bytes v0-v7 into them, storing the result back into v0-v7.
[all …]
/kernel/linux/linux-5.10/arch/arm64/crypto/
Dchacha-neon-core.S4 * Copyright (C) 2016-2018 Linaro, Ltd. <ard.biesheuvel@linaro.org>
11 * ChaCha20 256-bit cipher algorithm, RFC7539, x64 SSSE3 functions
29 * chacha_permute - permute one block
31 * Permute one 64-byte block where the state matrix is stored in the four NEON
32 * registers v0-v3. It performs matrix operations on four words in parallel,
46 add v0.4s, v0.4s, v1.4s
52 eor v4.16b, v1.16b, v2.16b
53 shl v1.4s, v4.4s, #12
54 sri v1.4s, v4.4s, #20
57 add v0.4s, v0.4s, v1.4s
[all …]
Daes-neonbs-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
10 * 'Faster and Timing-Attack Resistant AES-GCM' by Emilia Kaesper and
14 * for 32-bit ARM written by Andy Polyakov <appro@openssl.org>
215 ldp q18, q19, [bskey, #-96]
216 ldp q20, q21, [bskey, #-64]
217 ldp q22, q23, [bskey, #-32]
221 ldp q16, q17, [bskey, #-128]!
405 cmtst v1.16b, v7.16b, v9.16b
410 cmtst v6.16b, v7.16b, v14.16b
413 not v1.16b, v1.16b
[all …]
Daes-modes.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm64/crypto/aes-modes.S - chaining mode wrappers for AES
5 * Copyright (C) 2013 - 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
8 /* included by aes-ce.S and aes-neon.S */
26 encrypt_block4x v0, v1, v2, v3, w3, x2, x8, w7
31 decrypt_block4x v0, v1, v2, v3, w3, x2, x8, w7
37 encrypt_block5x v0, v1, v2, v3, v4, w3, x2, x8, w7
42 decrypt_block5x v0, v1, v2, v3, v4, w3, x2, x8, w7
55 stp x29, x30, [sp, #-16]!
63 ld1 {v0.16b-v3.16b}, [x1], #64 /* get 4 pt blocks */
[all …]
Dsha3-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha3-ce-core.S - core SHA-3 transform using v8.2 Crypto Extensions
46 ld1 { v0.1d- v3.1d}, [x0]
47 ld1 { v4.1d- v7.1d}, [x8], #32
48 ld1 { v8.1d-v11.1d}, [x8], #32
49 ld1 {v12.1d-v15.1d}, [x8], #32
50 ld1 {v16.1d-v19.1d}, [x8], #32
51 ld1 {v20.1d-v23.1d}, [x8], #32
59 ld1 {v25.8b-v28.8b}, [x1], #32
60 ld1 {v29.8b-v31.8b}, [x1], #24
[all …]
Dcrct10dif-ce-core.S2 // Accelerated CRC-T10DIF using arm64 NEON and Crypto Extensions instructions
14 // Implement fast CRC-T10DIF computation with SSE and PCLMULQDQ instructions
62 // /white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf
69 .arch armv8-a+crypto
276 CPU_LE( rev64 v1.16b, v1.16b )
281 CPU_LE( rev64 v6.16b, v6.16b )
284 CPU_LE( ext v1.16b, v1.16b, v1.16b, #8 )
289 CPU_LE( ext v6.16b, v6.16b, v6.16b, #8 )
305 // While >= 128 data bytes remain (not counting v0-v7), fold the 128
306 // bytes v0-v7 into them, storing the result back into v0-v7.
[all …]
Dsha256-core.S_shipped1 // SPDX-License-Identifier: GPL-2.0
11 // Copyright 2014-2016 The OpenSSL Project Authors. All Rights Reserved.
30 // SHA256-hw SHA256(*) SHA512
31 // Apple A7 1.97 10.5 (+33%) 6.73 (-1%(**))
32 // Cortex-A53 2.38 15.5 (+115%) 10.0 (+150%(***))
33 // Cortex-A57 2.31 11.6 (+86%) 7.51 (+260%(***))
35 // X-Gene 20.0 (+100%) 12.8 (+300%(***))
40 // (**) The result is a trade-off: it's possible to improve it by
42 // on Cortex-A53 (or by 4 cycles per round).
43 // (***) Super-impressive coefficients over gcc-generated code are
[all …]
/kernel/linux/linux-5.10/drivers/char/mwave/
Dmwavedd.h3 * mwavedd.h -- declarations for mwave device driver
23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
42 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
45 * 10/23/2000 - Alpha Release
79 #define PRINTK_2(f,s,v1) \ argument
81 printk(s,v1); \
84 #define PRINTK_3(f,s,v1,v2) \ argument
86 printk(s,v1,v2); \
89 #define PRINTK_4(f,s,v1,v2,v3) \ argument
91 printk(s,v1,v2,v3); \
[all …]
/kernel/linux/linux-6.6/drivers/char/mwave/
Dmwavedd.h3 * mwavedd.h -- declarations for mwave device driver
23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
42 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
45 * 10/23/2000 - Alpha Release
79 #define PRINTK_2(f,s,v1) \ argument
81 printk(s,v1); \
84 #define PRINTK_3(f,s,v1,v2) \ argument
86 printk(s,v1,v2); \
89 #define PRINTK_4(f,s,v1,v2,v3) \ argument
91 printk(s,v1,v2,v3); \
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
Datombios_crtc.c2 * Copyright 2007-8 Advanced Micro Devices, Inc.
32 #include "atom-bits.h"
43 struct drm_device *dev = crtc->dev; in amdgpu_atombios_crtc_overscan_setup()
52 args.ucCRTC = amdgpu_crtc->crtc_id; in amdgpu_atombios_crtc_overscan_setup()
54 switch (amdgpu_crtc->rmx_type) { in amdgpu_atombios_crtc_overscan_setup()
56 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup()
57 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup()
58 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup()
59 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup()
62 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; in amdgpu_atombios_crtc_overscan_setup()
[all …]
Datombios_encoders.c2 * Copyright 2007-11 Advanced Micro Devices, Inc.
72 struct drm_device *dev = amdgpu_encoder->base.dev; in amdgpu_atombios_encoder_get_backlight_level()
75 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) in amdgpu_atombios_encoder_get_backlight_level()
85 struct drm_encoder *encoder = &amdgpu_encoder->base; in amdgpu_atombios_encoder_set_backlight_level()
86 struct drm_device *dev = amdgpu_encoder->base.dev; in amdgpu_atombios_encoder_set_backlight_level()
90 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) in amdgpu_atombios_encoder_set_backlight_level()
93 if ((amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && in amdgpu_atombios_encoder_set_backlight_level()
94 amdgpu_encoder->enc_priv) { in amdgpu_atombios_encoder_set_backlight_level()
95 dig = amdgpu_encoder->enc_priv; in amdgpu_atombios_encoder_set_backlight_level()
96 dig->backlight_level = level; in amdgpu_atombios_encoder_set_backlight_level()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
Datombios_crtc.c2 * Copyright 2007-8 Advanced Micro Devices, Inc.
31 #include "atom-bits.h"
42 struct drm_device *dev = crtc->dev; in amdgpu_atombios_crtc_overscan_setup()
51 args.ucCRTC = amdgpu_crtc->crtc_id; in amdgpu_atombios_crtc_overscan_setup()
53 switch (amdgpu_crtc->rmx_type) { in amdgpu_atombios_crtc_overscan_setup()
55 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup()
56 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup()
57 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup()
58 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup()
61 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; in amdgpu_atombios_crtc_overscan_setup()
[all …]
Datombios_encoders.c2 * Copyright 2007-11 Advanced Micro Devices, Inc.
73 struct drm_device *dev = amdgpu_encoder->base.dev; in amdgpu_atombios_encoder_get_backlight_level()
76 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) in amdgpu_atombios_encoder_get_backlight_level()
86 struct drm_encoder *encoder = &amdgpu_encoder->base; in amdgpu_atombios_encoder_set_backlight_level()
87 struct drm_device *dev = amdgpu_encoder->base.dev; in amdgpu_atombios_encoder_set_backlight_level()
91 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) in amdgpu_atombios_encoder_set_backlight_level()
94 if ((amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && in amdgpu_atombios_encoder_set_backlight_level()
95 amdgpu_encoder->enc_priv) { in amdgpu_atombios_encoder_set_backlight_level()
96 dig = amdgpu_encoder->enc_priv; in amdgpu_atombios_encoder_set_backlight_level()
97 dig->backlight_level = level; in amdgpu_atombios_encoder_set_backlight_level()
[all …]
/kernel/linux/linux-5.10/arch/s390/crypto/
Dcrc32le-vx.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Hardware-accelerated CRC-32 variants for Linux on z Systems
6 * computing of bitreflected CRC-32 checksums for IEEE 802.3 Ethernet
9 * This CRC-32 implementation algorithm is bitreflected and processes
10 * the least-significant bit first (Little-Endian).
17 #include <asm/nospec-insn.h>
18 #include <asm/vx-insn.h>
20 /* Vector register range containing CRC-32 constants */
32 * The CRC-32 constant block contains reduction constants to fold and
35 * For the CRC-32 variants, the constants are precomputed according to
[all …]
/kernel/linux/linux-6.6/arch/s390/crypto/
Dcrc32le-vx.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Hardware-accelerated CRC-32 variants for Linux on z Systems
6 * computing of bitreflected CRC-32 checksums for IEEE 802.3 Ethernet
9 * This CRC-32 implementation algorithm is bitreflected and processes
10 * the least-significant bit first (Little-Endian).
17 #include <asm/nospec-insn.h>
18 #include <asm/vx-insn.h>
20 /* Vector register range containing CRC-32 constants */
32 * The CRC-32 constant block contains reduction constants to fold and
35 * For the CRC-32 variants, the constants are precomputed according to
[all …]

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