| /kernel/linux/linux-6.6/Documentation/admin-guide/hw-vuln/ |
| D | indirect-target-selection.rst | 26 Affected CPUs
28 Below is the list of ITS affected CPUs [#f2]_ [#f3]_:
34 SKYLAKE_X (step >= 6) 06_55H Affected Affected
35 ICELAKE_X 06_6AH Not affected Affected
36 ICELAKE_D 06_6CH Not affected Affected
37 ICELAKE_L 06_7EH Not affected Affected
38 TIGERLAKE_L 06_8CH Not affected Affected
39 TIGERLAKE 06_8DH Not affected Affected
40 KABYLAKE_L (step >= 12) 06_8EH Affected Affected
41 KABYLAKE (step >= 13) 06_9EH Affected Affected
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| D | reg-file-data-sampling.rst | 11 Affected Processors
13 Below is the list of affected Intel processors [#f1]_:
33 RAPTORLAKE(06_B7H) codenamed Catlow are not affected. They are reported as
34 vulnerable in Linux because they share the same family/model with an affected
35 part. Unlike their affected counterparts, they do not enumerate RFDS_CLEAR or
37 affected and unaffected parts, but it is deemed not worth adding complexity as
44 mitigation strategy to force the CPU to clear the affected buffers before an
47 The microcode clears the affected CPU buffers when the VERW instruction is
53 before VMentry. None of the affected cores support SMT, so VERW is not required
58 Newer processors and microcode update on existing affected processors added new
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| D | processor_mmio_stale_data.rst | 9 are not affected. System environments using virtualization where MMIO access is
61 processors affected by FBSDP, this may expose stale data from the fill buffers
67 into client core fill buffers, processors affected by MFBDS can leak data from
77 Affected Processors
79 Not all the CPUs are affected by all the variants. For instance, most
83 Below is the list of affected Intel processors [#f1]_:
108 If a CPU is in the affected processor list, but not affected by a variant, it
115 Newer processors and microcode update on existing affected processors added new
122 Bit 13 - SBDR_SSDP_NO - When set, processor is not affected by either the
125 Bit 14 - FBSDP_NO - When set, processor is not affected by the Fill Buffer
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| D | mds.rst | 8 Affected processors
23 Whether a processor is affected or not can be read out from the MDS
26 Not all processors are affected by all variants of MDS, but the mitigation
100 * - 'Not affected'
143 The kernel detects the affected CPUs and the presence of the microcode
146 If a CPU is affected and the microcode is available, then the kernel
156 The mitigation for MDS clears the affected CPU buffers on return to user
160 is only affected by MSBDS and not any other MDS variant, because the
163 For CPUs which are only affected by MSBDS the user space, guest and idle
164 transition mitigations are sufficient and SMT is not affected.
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| D | tsx_async_abort.rst | 10 Affected processors
19 Whether a processor is affected or not can be read out from the TAA
99 …- The CPU is affected by this vulnerability and the microcode and kernel mitigation are not applie…
106 * - 'Not affected'
107 - The CPU is not affected by this issue.
131 The kernel detects the affected CPUs and the presence of the microcode which is
132 required. If a CPU is affected and the microcode is available, then the kernel
142 Affected systems where the host has TAA microcode and TAA is mitigated by
159 off This option disables the TAA mitigation on affected platforms.
161 is affected, the system is vulnerable.
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| D | special-register-buffer-data-sampling.rst | 17 Affected processors
20 be affected.
22 A processor is affected by SRBDS if its Family_Model and stepping is
25 latter class of processors are only affected when Intel TSX is enabled
26 by software using TSX_CTRL_MSR otherwise they are not affected.
118 affected platforms.
130 Not affected Processor not vulnerable
141 affected but with no way to know if host
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| D | cross-thread-rsb.rst | 18 Affected processors
38 Affected SMT-capable processors support 1T and 2T modes of execution when SMT
46 In affected processors, the return address predictor (RAP) is partitioned
61 An attack can be mounted on affected processors by performing a series of CALL
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| /kernel/linux/linux-5.10/Documentation/admin-guide/hw-vuln/ |
| D | reg-file-data-sampling.rst | 11 Affected Processors
13 Below is the list of affected Intel processors [#f1]_:
33 RAPTORLAKE(06_B7H) codenamed Catlow are not affected. They are reported as
34 vulnerable in Linux because they share the same family/model with an affected
35 part. Unlike their affected counterparts, they do not enumerate RFDS_CLEAR or
37 affected and unaffected parts, but it is deemed not worth adding complexity as
44 mitigation strategy to force the CPU to clear the affected buffers before an
47 The microcode clears the affected CPU buffers when the VERW instruction is
53 before VMentry. None of the affected cores support SMT, so VERW is not required
58 Newer processors and microcode update on existing affected processors added new
[all …]
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| D | processor_mmio_stale_data.rst | 9 are not affected. System environments using virtualization where MMIO access is
61 processors affected by FBSDP, this may expose stale data from the fill buffers
67 into client core fill buffers, processors affected by MFBDS can leak data from
77 Affected Processors
79 Not all the CPUs are affected by all the variants. For instance, most
83 Below is the list of affected Intel processors [#f1]_:
108 If a CPU is in the affected processor list, but not affected by a variant, it
115 Newer processors and microcode update on existing affected processors added new
122 Bit 13 - SBDR_SSDP_NO - When set, processor is not affected by either the
125 Bit 14 - FBSDP_NO - When set, processor is not affected by the Fill Buffer
[all …]
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| D | mds.rst | 8 Affected processors
23 Whether a processor is affected or not can be read out from the MDS
26 Not all processors are affected by all variants of MDS, but the mitigation
100 * - 'Not affected'
143 The kernel detects the affected CPUs and the presence of the microcode
146 If a CPU is affected and the microcode is available, then the kernel
156 The mitigation for MDS clears the affected CPU buffers on return to user
160 is only affected by MSBDS and not any other MDS variant, because the
163 For CPUs which are only affected by MSBDS the user space, guest and idle
164 transition mitigations are sufficient and SMT is not affected.
[all …]
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| D | tsx_async_abort.rst | 10 Affected processors
19 Whether a processor is affected or not can be read out from the TAA
99 …- The CPU is affected by this vulnerability and the microcode and kernel mitigation are not applie…
106 * - 'Not affected'
107 - The CPU is not affected by this issue.
131 The kernel detects the affected CPUs and the presence of the microcode which is
132 required. If a CPU is affected and the microcode is available, then the kernel
142 Affected systems where the host has TAA microcode and TAA is mitigated by
159 off This option disables the TAA mitigation on affected platforms.
161 is affected, the system is vulnerable.
[all …]
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| D | special-register-buffer-data-sampling.rst | 16 Affected processors
19 be affected.
21 A processor is affected by SRBDS if its Family_Model and stepping is
24 latter class of processors are only affected when Intel TSX is enabled
25 by software using TSX_CTRL_MSR otherwise they are not affected.
117 affected platforms.
129 Not affected Processor not vulnerable
140 affected but with no way to know if host
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| /kernel/linux/linux-5.10/arch/x86/kernel/ |
| D | smp.c | 67 * 5AP. symmetric IO mode (normal Linux operation) not affected.
69 * 6AP. 'noapic' mode might be affected - fixed in later steppings
92 * 6AP. not affected - worked around in hardware
93 * 7AP. not affected - worked around in hardware
95 * 9AP. only 'noapic' mode affected. Might generate spurious
98 * 10AP. not affected - worked around in hardware
102 * 12AP. not affected - worked around in hardware
103 * 13AP. not affected - worked around in hardware
105 * 15AP. not affected - worked around in hardware
106 * 16AP. not affected - worked around in hardware
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| /kernel/linux/linux-6.6/Documentation/arch/x86/ |
| D | mds.rst | 74 thread case (SMT off): Force the CPU to clear the affected buffers.
78 the affected CPU buffers when the VERW instruction is executed.
83 VERW can be avoided. If the CPU is not affected by L1TF then VERW needs to
119 off Mitigation is disabled. Either the CPU is not affected or
122 full Mitigation is enabled. CPU is affected and MD_CLEAR is
125 vmwerv Mitigation is enabled. CPU is affected and MD_CLEAR is not
132 If the CPU is affected and mds=off is not supplied on the kernel command
143 on affected CPUs when the mitigation is not disabled on the kernel
174 cleared on affected CPUs when SMT is active. This addresses the
181 The idle clearing is enabled on CPUs which are only affected by MSBDS
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| /kernel/linux/linux-6.6/arch/x86/kernel/ |
| D | smp.c | 69 * 5AP. symmetric IO mode (normal Linux operation) not affected.
71 * 6AP. 'noapic' mode might be affected - fixed in later steppings
94 * 6AP. not affected - worked around in hardware
95 * 7AP. not affected - worked around in hardware
97 * 9AP. only 'noapic' mode affected. Might generate spurious
100 * 10AP. not affected - worked around in hardware
104 * 12AP. not affected - worked around in hardware
105 * 13AP. not affected - worked around in hardware
107 * 15AP. not affected - worked around in hardware
108 * 16AP. not affected - worked around in hardware
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| /kernel/linux/linux-5.10/Documentation/x86/ |
| D | mds.rst | 74 thread case (SMT off): Force the CPU to clear the affected buffers.
78 the affected CPU buffers when the VERW instruction is executed.
83 VERW can be avoided. If the CPU is not affected by L1TF then VERW needs to
119 off Mitigation is disabled. Either the CPU is not affected or
122 full Mitigation is enabled. CPU is affected and MD_CLEAR is
125 vmwerv Mitigation is enabled. CPU is affected and MD_CLEAR is not
132 If the CPU is affected and mds=off is not supplied on the kernel command
143 on affected CPUs when the mitigation is not disabled on the kernel
174 cleared on affected CPUs when SMT is active. This addresses the
181 The idle clearing is enabled on CPUs which are only affected by MSBDS
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| /kernel/linux/linux-6.6/arch/arm64/ |
| D | Kconfig | 424 The affected design reports FEAT_HAFDBS as not implemented in
457 the kernel if an affected CPU is detected.
479 the kernel if an affected CPU is detected.
502 only patch the kernel if an affected CPU is detected.
524 the kernel if an affected CPU is detected.
535 Affected Cortex-A57 parts might deadlock when exclusive load/store
542 the kernel if an affected CPU is detected.
554 Affected Cortex-A57 parts might report a Stage 2 translation
563 the kernel if an affected CPU is detected.
575 Affected parts may corrupt the AES state if an interrupt is
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| /kernel/linux/linux-5.10/drivers/base/ |
| D | cpu.c | 556 return sysfs_emit(buf, "Not affected\n"); in cpu_show_meltdown()
562 return sysfs_emit(buf, "Not affected\n"); in cpu_show_spectre_v1()
568 return sysfs_emit(buf, "Not affected\n"); in cpu_show_spectre_v2()
574 return sysfs_emit(buf, "Not affected\n"); in cpu_show_spec_store_bypass()
580 return sysfs_emit(buf, "Not affected\n"); in cpu_show_l1tf()
586 return sysfs_emit(buf, "Not affected\n"); in cpu_show_mds()
593 return sysfs_emit(buf, "Not affected\n"); in cpu_show_tsx_async_abort()
599 return sysfs_emit(buf, "Not affected\n"); in cpu_show_itlb_multihit()
605 return sysfs_emit(buf, "Not affected\n"); in cpu_show_srbds()
611 return sysfs_emit(buf, "Not affected\n"); in cpu_show_mmio_stale_data()
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| /kernel/linux/linux-5.10/security/integrity/evm/ |
| D | evm_main.c | 293 * @dentry: pointer to the affected dentry
367 * @dentry: pointer to the affected dentry
368 * @xattr_name: pointer to the affected extended attribute name
402 * @dentry: pointer to the affected dentry
403 * @xattr_name: pointer to the affected extended attribute name
430 * @dentry: pointer to the affected dentry
431 * @xattr_name: pointer to the affected extended attribute name
455 * @dentry: pointer to the affected dentry
456 * @xattr_name: pointer to the affected extended attribute name
476 * @dentry: pointer to the affected dentry
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| /kernel/linux/linux-5.10/arch/alpha/kernel/ |
| D | bugs.c | 25 return sprintf(buf, "Not affected\n"); in cpu_show_meltdown()
34 return sprintf(buf, "Not affected\n"); in cpu_show_spectre_v1()
43 return sprintf(buf, "Not affected\n"); in cpu_show_spectre_v2()
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| /kernel/linux/linux-6.6/arch/alpha/kernel/ |
| D | bugs.c | 25 return sprintf(buf, "Not affected\n"); in cpu_show_meltdown()
34 return sprintf(buf, "Not affected\n"); in cpu_show_spectre_v1()
43 return sprintf(buf, "Not affected\n"); in cpu_show_spectre_v2()
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| /kernel/linux/linux-6.6/security/integrity/evm/ |
| D | evm_main.c | 424 * @dentry: pointer to the affected dentry
441 * @dentry: pointer to the affected dentry
558 * @dentry: pointer to the affected dentry
559 * @xattr_name: pointer to the affected extended attribute name
595 * @dentry: pointer to the affected dentry
596 * @xattr_name: pointer to the affected extended attribute name
645 * @dentry: pointer to the affected dentry
704 * @xattr_name: pointer to the affected extended attribute name
729 * @dentry: pointer to the affected dentry
730 * @xattr_name: pointer to the affected extended attribute name
[all …]
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| /kernel/linux/linux-6.6/include/linux/ |
| D | cpu_pm.h | 28 * CPU notifications apply to a single CPU and must be called on the affected
29 * CPU. They are used to save per-cpu context for affected blocks.
32 * are used to save any global context for affected blocks, and must be called
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| /kernel/linux/linux-5.10/include/linux/ |
| D | cpu_pm.h | 28 * CPU notifications apply to a single CPU and must be called on the affected
29 * CPU. They are used to save per-cpu context for affected blocks.
32 * are used to save any global context for affected blocks, and must be called
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| /kernel/linux/linux-5.10/arch/arm64/ |
| D | Kconfig | 381 the kernel if an affected CPU is detected.
403 the kernel if an affected CPU is detected.
426 only patch the kernel if an affected CPU is detected.
448 the kernel if an affected CPU is detected.
459 Affected Cortex-A57 parts might deadlock when exclusive load/store
466 the kernel if an affected CPU is detected.
478 Affected Cortex-A57 parts might report a Stage 2 translation
487 the kernel if an affected CPU is detected.
499 Affected parts may corrupt the AES state if an interrupt is
515 When running a compat (AArch32) userspace on an affected Cortex-A53
[all …]
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