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/kernel/linux/linux-6.6/drivers/amba/
Dtegra-ahb.c21 #include <soc/tegra/ahb.h>
23 #define DRV_NAME "tegra-ahb"
79 * 0x4 for the AHB IP block. According to the TRM, the low byte
126 static inline u32 gizmo_readl(struct tegra_ahb *ahb, u32 offset) in gizmo_readl() argument
128 return readl(ahb->regs + offset); in gizmo_readl()
131 static inline void gizmo_writel(struct tegra_ahb *ahb, u32 value, u32 offset) in gizmo_writel() argument
133 writel(value, ahb->regs + offset); in gizmo_writel()
141 struct tegra_ahb *ahb; in tegra_ahb_enable_smmu() local
146 ahb = dev_get_drvdata(dev); in tegra_ahb_enable_smmu()
147 val = gizmo_readl(ahb, AHB_ARBITRATION_XBAR_CTRL); in tegra_ahb_enable_smmu()
[all …]
/kernel/linux/linux-5.10/drivers/amba/
Dtegra-ahb.c21 #include <soc/tegra/ahb.h>
23 #define DRV_NAME "tegra-ahb"
79 * 0x4 for the AHB IP block. According to the TRM, the low byte
126 static inline u32 gizmo_readl(struct tegra_ahb *ahb, u32 offset) in gizmo_readl() argument
128 return readl(ahb->regs + offset); in gizmo_readl()
131 static inline void gizmo_writel(struct tegra_ahb *ahb, u32 value, u32 offset) in gizmo_writel() argument
133 writel(value, ahb->regs + offset); in gizmo_writel()
141 struct tegra_ahb *ahb; in tegra_ahb_enable_smmu() local
146 ahb = dev_get_drvdata(dev); in tegra_ahb_enable_smmu()
147 val = gizmo_readl(ahb, AHB_ARBITRATION_XBAR_CTRL); in tegra_ahb_enable_smmu()
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/tegra/
Dnvidia,tegra20-ahb.yaml4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-ahb.yaml#
11 title: NVIDIA Tegra AHB
17 - nvidia,tegra20-ahb
18 - nvidia,tegra30-ahb
21 - nvidia,tegra114-ahb
22 - nvidia,tegra124-ahb
23 - nvidia,tegra210-ahb
24 - const: nvidia,tegra30-ahb
37 ahb@6000c004 {
38 compatible = "nvidia,tegra20-ahb";
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra20-ahb.txt1 NVIDIA Tegra AHB
4 - compatible : For Tegra20, must contain "nvidia,tegra20-ahb". For
5 Tegra30, must contain "nvidia,tegra30-ahb". Otherwise, must contain
6 '"nvidia,<chip>-ahb", "nvidia,tegra30-ahb"' where <chip> is tegra124,
14 ahb: ahb@6000c004 {
15 compatible = "nvidia,tegra20-ahb";
16 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
/kernel/linux/linux-5.10/drivers/clk/imx/
Dclk-imx35.c34 unsigned char arm, ahb, sel; member
38 { .arm = 1, .ahb = 4, .sel = 0},
39 { .arm = 1, .ahb = 3, .sel = 1},
40 { .arm = 2, .ahb = 2, .sel = 0},
41 { .arm = 0, .ahb = 0, .sel = 0},
42 { .arm = 0, .ahb = 0, .sel = 0},
43 { .arm = 0, .ahb = 0, .sel = 0},
44 { .arm = 4, .ahb = 1, .sel = 0},
45 { .arm = 1, .ahb = 5, .sel = 0},
46 { .arm = 1, .ahb = 8, .sel = 0},
[all …]
Dclk-imx27.c41 "ahb", "ipg", "per1_div", "per2_div",
70 clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2); in _mx27_clocks_init()
71 clk[IMX27_CLK_IPG] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); in _mx27_clocks_init()
73 clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4); in _mx27_clocks_init()
74 clk[IMX27_CLK_IPG] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1); in _mx27_clocks_init()
77 clk[IMX27_CLK_MSHC_DIV] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6); in _mx27_clocks_init()
78 clk[IMX27_CLK_NFC_DIV] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4); in _mx27_clocks_init()
140 clk[IMX27_CLK_USB_AHB_GATE] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11); in _mx27_clocks_init()
141 clk[IMX27_CLK_SLCDC_AHB_GATE] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12); in _mx27_clocks_init()
142 clk[IMX27_CLK_SAHARA_AHB_GATE] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13); in _mx27_clocks_init()
[all …]
Dclk-imx25.c46 static const char *per_sel_clks[] = { "ahb", "upll", };
47 static const char *cko_sel_clks[] = { "dummy", "osc", "cpu", "ahb",
53 dummy, osc, mpll, upll, mpll_cpu_3_4, cpu_sel, cpu, ahb, usb_div, ipg, enumerator
86 clk[ahb] = imx_clk_divider("ahb", "cpu", ccm(CCM_CCTL), 28, 2); in __mx25_clocks_init()
88 clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); in __mx25_clocks_init()
140 clk[ata_ahb] = imx_clk_gate("ata_ahb", "ahb", ccm(CCM_CGCR0), 16); in __mx25_clocks_init()
142 clk[csi_ahb] = imx_clk_gate("csi_ahb", "ahb", ccm(CCM_CGCR0), 18); in __mx25_clocks_init()
143 clk[emi_ahb] = imx_clk_gate("emi_ahb", "ahb", ccm(CCM_CGCR0), 19); in __mx25_clocks_init()
144 clk[esai_ahb] = imx_clk_gate("esai_ahb", "ahb", ccm(CCM_CGCR0), 20); in __mx25_clocks_init()
145 clk[esdhc1_ahb] = imx_clk_gate("esdhc1_ahb", "ahb", ccm(CCM_CGCR0), 21); in __mx25_clocks_init()
[all …]
/kernel/linux/linux-6.6/drivers/clk/imx/
Dclk-imx35.c33 unsigned char arm, ahb, sel; member
37 { .arm = 1, .ahb = 4, .sel = 0},
38 { .arm = 1, .ahb = 3, .sel = 1},
39 { .arm = 2, .ahb = 2, .sel = 0},
40 { .arm = 0, .ahb = 0, .sel = 0},
41 { .arm = 0, .ahb = 0, .sel = 0},
42 { .arm = 0, .ahb = 0, .sel = 0},
43 { .arm = 4, .ahb = 1, .sel = 0},
44 { .arm = 1, .ahb = 5, .sel = 0},
45 { .arm = 1, .ahb = 8, .sel = 0},
[all …]
Dclk-imx27.c40 "ahb", "ipg", "per1_div", "per2_div",
69 clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2); in _mx27_clocks_init()
70 clk[IMX27_CLK_IPG] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); in _mx27_clocks_init()
72 clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4); in _mx27_clocks_init()
73 clk[IMX27_CLK_IPG] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1); in _mx27_clocks_init()
76 clk[IMX27_CLK_MSHC_DIV] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6); in _mx27_clocks_init()
77 clk[IMX27_CLK_NFC_DIV] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4); in _mx27_clocks_init()
139 clk[IMX27_CLK_USB_AHB_GATE] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11); in _mx27_clocks_init()
140 clk[IMX27_CLK_SLCDC_AHB_GATE] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12); in _mx27_clocks_init()
141 clk[IMX27_CLK_SAHARA_AHB_GATE] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13); in _mx27_clocks_init()
[all …]
Dclk-imx25.c47 static const char *per_sel_clks[] = { "ahb", "upll", };
48 static const char *cko_sel_clks[] = { "dummy", "osc", "cpu", "ahb",
54 dummy, osc, mpll, upll, mpll_cpu_3_4, cpu_sel, cpu, ahb, usb_div, ipg, enumerator
87 clk[ahb] = imx_clk_divider("ahb", "cpu", ccm(CCM_CCTL), 28, 2); in __mx25_clocks_init()
89 clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); in __mx25_clocks_init()
141 clk[ata_ahb] = imx_clk_gate("ata_ahb", "ahb", ccm(CCM_CGCR0), 16); in __mx25_clocks_init()
143 clk[csi_ahb] = imx_clk_gate("csi_ahb", "ahb", ccm(CCM_CGCR0), 18); in __mx25_clocks_init()
144 clk[emi_ahb] = imx_clk_gate("emi_ahb", "ahb", ccm(CCM_CGCR0), 19); in __mx25_clocks_init()
145 clk[esai_ahb] = imx_clk_gate("esai_ahb", "ahb", ccm(CCM_CGCR0), 20); in __mx25_clocks_init()
146 clk[esdhc1_ahb] = imx_clk_gate("esdhc1_ahb", "ahb", ccm(CCM_CGCR0), 21); in __mx25_clocks_init()
[all …]
/kernel/linux/linux-6.6/drivers/clk/sunxi-ng/
Dccu-sun4i-a10.c246 .hw.init = CLK_HW_INIT("ahb", "axi", &ccu_div_ops, 0),
267 .hw.init = CLK_HW_INIT_PARENTS("ahb",
281 static SUNXI_CCU_DIV_TABLE(apb0_clk, "apb0", "ahb",
292 static SUNXI_CCU_GATE(axi_dram_clk, "axi-dram", "ahb",
295 static SUNXI_CCU_GATE(ahb_otg_clk, "ahb-otg", "ahb",
297 static SUNXI_CCU_GATE(ahb_ehci0_clk, "ahb-ehci0", "ahb",
299 static SUNXI_CCU_GATE(ahb_ohci0_clk, "ahb-ohci0", "ahb",
301 static SUNXI_CCU_GATE(ahb_ehci1_clk, "ahb-ehci1", "ahb",
303 static SUNXI_CCU_GATE(ahb_ohci1_clk, "ahb-ohci1", "ahb",
305 static SUNXI_CCU_GATE(ahb_ss_clk, "ahb-ss", "ahb",
[all …]
Dccu-sun5i.c214 .hw.init = CLK_HW_INIT_PARENTS("ahb",
228 static SUNXI_CCU_DIV_TABLE(apb0_clk, "apb0", "ahb",
241 static SUNXI_CCU_GATE(ahb_otg_clk, "ahb-otg", "ahb",
243 static SUNXI_CCU_GATE(ahb_ehci_clk, "ahb-ehci", "ahb",
245 static SUNXI_CCU_GATE(ahb_ohci_clk, "ahb-ohci", "ahb",
247 static SUNXI_CCU_GATE(ahb_ss_clk, "ahb-ss", "ahb",
249 static SUNXI_CCU_GATE(ahb_dma_clk, "ahb-dma", "ahb",
251 static SUNXI_CCU_GATE(ahb_bist_clk, "ahb-bist", "ahb",
253 static SUNXI_CCU_GATE(ahb_mmc0_clk, "ahb-mmc0", "ahb",
255 static SUNXI_CCU_GATE(ahb_mmc1_clk, "ahb-mmc1", "ahb",
[all …]
/kernel/linux/linux-5.10/drivers/clk/sunxi-ng/
Dccu-sun4i-a10.c244 .hw.init = CLK_HW_INIT("ahb", "axi", &ccu_div_ops, 0),
265 .hw.init = CLK_HW_INIT_PARENTS("ahb",
279 static SUNXI_CCU_DIV_TABLE(apb0_clk, "apb0", "ahb",
290 static SUNXI_CCU_GATE(axi_dram_clk, "axi-dram", "ahb",
293 static SUNXI_CCU_GATE(ahb_otg_clk, "ahb-otg", "ahb",
295 static SUNXI_CCU_GATE(ahb_ehci0_clk, "ahb-ehci0", "ahb",
297 static SUNXI_CCU_GATE(ahb_ohci0_clk, "ahb-ohci0", "ahb",
299 static SUNXI_CCU_GATE(ahb_ehci1_clk, "ahb-ehci1", "ahb",
301 static SUNXI_CCU_GATE(ahb_ohci1_clk, "ahb-ohci1", "ahb",
303 static SUNXI_CCU_GATE(ahb_ss_clk, "ahb-ss", "ahb",
[all …]
Dccu-sun5i.c214 .hw.init = CLK_HW_INIT_PARENTS("ahb",
228 static SUNXI_CCU_DIV_TABLE(apb0_clk, "apb0", "ahb",
241 static SUNXI_CCU_GATE(ahb_otg_clk, "ahb-otg", "ahb",
243 static SUNXI_CCU_GATE(ahb_ehci_clk, "ahb-ehci", "ahb",
245 static SUNXI_CCU_GATE(ahb_ohci_clk, "ahb-ohci", "ahb",
247 static SUNXI_CCU_GATE(ahb_ss_clk, "ahb-ss", "ahb",
249 static SUNXI_CCU_GATE(ahb_dma_clk, "ahb-dma", "ahb",
251 static SUNXI_CCU_GATE(ahb_bist_clk, "ahb-bist", "ahb",
253 static SUNXI_CCU_GATE(ahb_mmc0_clk, "ahb-mmc0", "ahb",
255 static SUNXI_CCU_GATE(ahb_mmc1_clk, "ahb-mmc1", "ahb",
[all …]
/kernel/linux/linux-6.6/drivers/clk/microchip/
Dclk-mpfs.c269 * peripheral clocks - devices connected to axi or ahb buses.
288 * - CLK_RTC: the onboard RTC's AHB bus clock must be kept running as the rtc will stop
289 * if the AHB interface clock is disabled
297 CLK_PERIPH(CLK_ENVM, "clk_periph_envm", PARENT_CLK(AHB), 0, CLK_IS_CRITICAL),
298 CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", PARENT_CLK(AHB), 1, 0),
299 CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", PARENT_CLK(AHB), 2, 0),
300 CLK_PERIPH(CLK_MMC, "clk_periph_mmc", PARENT_CLK(AHB), 3, 0),
302 CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", PARENT_CLK(AHB), 5, CLK_IS_CRITICAL),
303 CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", PARENT_CLK(AHB), 6, 0),
304 CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", PARENT_CLK(AHB), 7, 0),
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dallwinner,sun5i-a13-ahb-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun5i-a13-ahb-clk.yaml#
7 title: Allwinner A13 AHB Clock
20 const: allwinner,sun5i-a13-ahb-clk
44 ahb@1c20054 {
46 compatible = "allwinner,sun5i-a13-ahb-clk";
49 clock-output-names = "ahb";
Dallwinner,sun4i-a10-ahb-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ahb-clk.yaml#
7 title: Allwinner A10 AHB Clock
21 - allwinner,sun4i-a10-ahb-clk
51 const: allwinner,sun4i-a10-ahb-clk
82 ahb@1c20054 {
84 compatible = "allwinner,sun4i-a10-ahb-clk";
87 clock-output-names = "ahb";
Dnspire-clock.txt5 "lsi,nspire-cx-ahb-divider" for the AHB divider in the CX model
6 "lsi,nspire-classic-ahb-divider" for the AHB divider in the older model
14 - clocks: For the "nspire-*-ahb-divider" compatible clocks, this is the parent
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dallwinner,sun5i-a13-ahb-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun5i-a13-ahb-clk.yaml#
7 title: Allwinner A13 AHB Clock Device Tree Bindings
20 const: allwinner,sun5i-a13-ahb-clk
44 ahb@1c20054 {
46 compatible = "allwinner,sun5i-a13-ahb-clk";
49 clock-output-names = "ahb";
Dallwinner,sun4i-a10-ahb-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ahb-clk.yaml#
7 title: Allwinner A10 AHB Clock Device Tree Bindings
21 - allwinner,sun4i-a10-ahb-clk
51 const: allwinner,sun4i-a10-ahb-clk
82 ahb@1c20054 {
84 compatible = "allwinner,sun4i-a10-ahb-clk";
87 clock-output-names = "ahb";
Dnspire-clock.txt5 "lsi,nspire-cx-ahb-divider" for the AHB divider in the CX model
6 "lsi,nspire-classic-ahb-divider" for the AHB divider in the older model
14 - clocks: For the "nspire-*-ahb-divider" compatible clocks, this is the parent
/kernel/linux/linux-6.6/drivers/clk/
Dclk-gemini.c93 { 2, "gmac0-gate", "ahb", 0 },
94 { 3, "gmac1-gate", "ahb", 0 },
95 { 4, "sata0-gate", "ahb", 0 },
96 { 5, "sata1-gate", "ahb", 0 },
97 { 6, "usb0-gate", "ahb", 0 },
98 { 7, "usb1-gate", "ahb", 0 },
99 { 8, "ide-gate", "ahb", 0 },
100 { 9, "pci-gate", "ahb", 0 },
105 { 10, "ddr-gate", "ahb", CLK_IS_CRITICAL },
110 { 11, "flash-gate", "ahb", CLK_IGNORE_UNUSED },
[all …]
/kernel/linux/linux-5.10/drivers/clk/
Dclk-gemini.c93 { 2, "gmac0-gate", "ahb", 0 },
94 { 3, "gmac1-gate", "ahb", 0 },
95 { 4, "sata0-gate", "ahb", 0 },
96 { 5, "sata1-gate", "ahb", 0 },
97 { 6, "usb0-gate", "ahb", 0 },
98 { 7, "usb1-gate", "ahb", 0 },
99 { 8, "ide-gate", "ahb", 0 },
100 { 9, "pci-gate", "ahb", 0 },
105 { 10, "ddr-gate", "ahb", CLK_IS_CRITICAL },
110 { 11, "flash-gate", "ahb", CLK_IGNORE_UNUSED },
[all …]
/kernel/linux/linux-6.6/drivers/dma/dw/
DKconfig12 tristate "Synopsys DesignWare AHB DMA platform driver"
16 Support the Synopsys DesignWare AHB DMA controller. This
25 the Synopsys DesignWare AHB DMA controller located on Renesas
29 tristate "Synopsys DesignWare AHB DMA PCI driver"
34 Support the Synopsys DesignWare AHB DMA controller on the
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/
Dqcom,pcie.txt86 - "iface" Configuration AHB clock
121 - "ahb" AHB clock
128 - "iface" AHB clock
156 - "ahb" AHB reset
181 - "ahb" AHB reset
182 - "phy_ahb" PHY AHB reset
194 - "ahb" AHB Reset
206 - "ahb" AHB reset
294 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";

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