Home
last modified time | relevance | path

Searched full:aon (Results 1 – 25 of 171) sorted by relevance

1234567

/kernel/linux/linux-5.10/drivers/pinctrl/zte/
Dpinctrl-zx.h22 * @aon_pin: whether it's an AON pin
26 * @coffset: pinconf register offset within AON controller
27 * @cbitpos: pinconf bit position within AON register
30 * Unlike TOP pinmux and AON pinconf registers which are arranged pretty
31 * arbitrarily, AON pinmux register bits are well organized per pin id, and
32 * each pin occupies two bits, so that we can calculate the AON register offset
34 * AON pinconf register data for the pin.
89 * When the flag is set, it's a mux configuration for an AON pin that sits in
90 * AON register. Otherwise, it's one for AON pin but sitting in TOP register.
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/timestamp/
Dnvidia,tegra194-hte.yaml19 GPIO lines from the AON (always on) GPIO controller.
24 - nvidia,tegra194-gte-aon
26 - nvidia,tegra234-gte-aon
49 property and the value depends on the HTE instance in the chip. The AON
57 The phandle to AON gpio controller instance. This is required to handle
80 - nvidia,tegra194-gte-aon
81 - nvidia,tegra234-gte-aon
114 - nvidia,tegra234-gte-aon
124 compatible = "nvidia,tegra194-gte-aon";
/kernel/linux/linux-5.10/drivers/clk/sprd/
Dsc9860-clk.c500 static SPRD_COMP_CLK(aon_apb, "aon-apb", aon_apb_parents, 0x230,
602 static SPRD_MUX_CLK(aon_i2c, "aon-i2c", cm3_i2c_parents, 0x280,
826 static SPRD_SC_GATE_CLK(avs_lit_eb, "avs-lit-eb", "aon-apb", 0x0,
828 static SPRD_SC_GATE_CLK(avs_big_eb, "avs-big-eb", "aon-apb", 0x0,
830 static SPRD_SC_GATE_CLK(ap_intc5_eb, "ap-intc5-eb", "aon-apb", 0x0,
832 static SPRD_SC_GATE_CLK(gpio_eb, "gpio-eb", "aon-apb", 0x0,
834 static SPRD_SC_GATE_CLK(pwm0_eb, "pwm0-eb", "aon-apb", 0x0,
836 static SPRD_SC_GATE_CLK(pwm1_eb, "pwm1-eb", "aon-apb", 0x0,
838 static SPRD_SC_GATE_CLK(pwm2_eb, "pwm2-eb", "aon-apb", 0x0,
840 static SPRD_SC_GATE_CLK(pwm3_eb, "pwm3-eb", "aon-apb", 0x0,
[all …]
/kernel/linux/linux-6.6/drivers/clk/sprd/
Dsc9860-clk.c500 static SPRD_COMP_CLK(aon_apb, "aon-apb", aon_apb_parents, 0x230,
602 static SPRD_MUX_CLK(aon_i2c, "aon-i2c", cm3_i2c_parents, 0x280,
826 static SPRD_SC_GATE_CLK(avs_lit_eb, "avs-lit-eb", "aon-apb", 0x0,
828 static SPRD_SC_GATE_CLK(avs_big_eb, "avs-big-eb", "aon-apb", 0x0,
830 static SPRD_SC_GATE_CLK(ap_intc5_eb, "ap-intc5-eb", "aon-apb", 0x0,
832 static SPRD_SC_GATE_CLK(gpio_eb, "gpio-eb", "aon-apb", 0x0,
834 static SPRD_SC_GATE_CLK(pwm0_eb, "pwm0-eb", "aon-apb", 0x0,
836 static SPRD_SC_GATE_CLK(pwm1_eb, "pwm1-eb", "aon-apb", 0x0,
838 static SPRD_SC_GATE_CLK(pwm2_eb, "pwm2-eb", "aon-apb", 0x0,
840 static SPRD_SC_GATE_CLK(pwm3_eb, "pwm3-eb", "aon-apb", 0x0,
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mips/brcm/
Dsoc.txt21 = Always-On control block (AON CTRL)
28 "brcm,bcm7425-aon-ctrl"
29 "brcm,bcm7429-aon-ctrl"
30 "brcm,bcm7435-aon-ctrl" and
31 "brcm,brcmstb-aon-ctrl"
32 - reg : the register start and length for the AON CTRL block
37 compatible = "brcm,bcm7425-aon-ctrl", "brcm,brcmstb-aon-ctrl";
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mips/brcm/
Dsoc.txt21 = Always-On control block (AON CTRL)
28 "brcm,bcm7425-aon-ctrl"
29 "brcm,bcm7429-aon-ctrl"
30 "brcm,bcm7435-aon-ctrl" and
31 "brcm,brcmstb-aon-ctrl"
32 - reg : the register start and length for the AON CTRL block
37 compatible = "brcm,bcm7425-aon-ctrl", "brcm,brcmstb-aon-ctrl";
/kernel/linux/linux-5.10/drivers/clk/ti/
Dclk-33xx.c159 "l3-aon-clkctrl:0000:19",
160 "l3-aon-clkctrl:0000:30",
165 "l3-aon-clkctrl:0000:20",
175 "l3-aon-clkctrl:0000:22",
200 { AM3_L3_AON_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l3-aon-clkctrl:0000:24" },
252 DT_CLK(NULL, "dbg_clka_ck", "l3-aon-clkctrl:0000:30"),
253 DT_CLK(NULL, "dbg_sysclk_ck", "l3-aon-clkctrl:0000:19"),
258 DT_CLK(NULL, "stm_clk_div_ck", "l3-aon-clkctrl:0000:27"),
259 DT_CLK(NULL, "stm_pmd_clock_mux_ck", "l3-aon-clkctrl:0000:22"),
260 DT_CLK(NULL, "trace_clk_div_ck", "l3-aon-clkctrl:0000:24"),
[all …]
/kernel/linux/linux-6.6/drivers/clk/ti/
Dclk-33xx.c151 "l3-aon-clkctrl:0000:19",
152 "l3-aon-clkctrl:0000:30",
157 "l3-aon-clkctrl:0000:20",
167 "l3-aon-clkctrl:0000:22",
192 { AM3_L3_AON_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l3-aon-clkctrl:0000:24" },
244 DT_CLK(NULL, "dbg_clka_ck", "l3-aon-clkctrl:0000:30"),
245 DT_CLK(NULL, "dbg_sysclk_ck", "l3-aon-clkctrl:0000:19"),
250 DT_CLK(NULL, "stm_clk_div_ck", "l3-aon-clkctrl:0000:27"),
251 DT_CLK(NULL, "stm_pmd_clock_mux_ck", "l3-aon-clkctrl:0000:22"),
252 DT_CLK(NULL, "trace_clk_div_ck", "l3-aon-clkctrl:0000:24"),
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dbrcm,kona-ccu.txt60 "brcm,bcm11351-aon-ccu"
75 aon hub_timer peri 0 BCM281XX_AON_CCU_HUB_TIMER
76 aon pmu_bsc peri 1 BCM281XX_AON_CCU_PMU_BSC
77 aon pmu_bsc_var peri 2 BCM281XX_AON_CCU_PMU_BSC_VAR
106 "brcm,bcm21664-aon-ccu"
120 aon hub_timer peri 0 BCM21664_AON_CCU_HUB_TIMER
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dbrcm,kona-ccu.txt60 "brcm,bcm11351-aon-ccu"
75 aon hub_timer peri 0 BCM281XX_AON_CCU_HUB_TIMER
76 aon pmu_bsc peri 1 BCM281XX_AON_CCU_PMU_BSC
77 aon pmu_bsc_var peri 2 BCM281XX_AON_CCU_PMU_BSC_VAR
106 "brcm,bcm21664-aon-ccu"
120 aon hub_timer peri 0 BCM21664_AON_CCU_HUB_TIMER
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/gpio/
Dnvidia,tegra186-gpio.yaml14 Tegra186 contains two GPIO controllers; a main controller and an "AON"
83 - nvidia,tegra186-gpio-aon
85 - nvidia,tegra194-gpio-aon
87 - nvidia,tegra234-gpio-aon
166 - nvidia,tegra186-gpio-aon
167 - nvidia,tegra194-gpio-aon
168 - nvidia,tegra234-gpio-aon
205 compatible = "nvidia,tegra186-gpio-aon";
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/
Dnvidia,tegra234-pinmux-aon.yaml4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra234-pinmux-aon.yaml#
7 title: NVIDIA Tegra234 AON Pinmux Controller
17 const: nvidia,tegra234-pinmux-aon
65 compatible = "nvidia,tegra234-pinmux-aon";
Dstarfive,jh7110-aon-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-aon-pinctrl.yaml#
7 title: StarFive JH7110 AON Pin Controller
22 const: starfive,jh7110-aon-pinctrl
103 compatible = "starfive,jh7110-aon-pinctrl";
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/
Dzte,sysctrl.txt18 - compatible = "zte,zx296718-aon-sysctrl"
22 aon_sysctrl: aon-sysctrl@116000 {
23 compatible = "zte,zx296718-aon-sysctrl", "syscon";
/kernel/linux/linux-5.10/drivers/clk/bcm/
Dclk-iproc-pll.c197 val = readl(pll->control_base + ctrl->aon.offset); in __pll_disable()
198 val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift; in __pll_disable()
199 iproc_pll_write(pll, pll->control_base, ctrl->aon.offset, val); in __pll_disable()
204 val = readl(pll->pwr_base + ctrl->aon.offset); in __pll_disable()
205 val |= 1 << ctrl->aon.iso_shift; in __pll_disable()
206 iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); in __pll_disable()
209 val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); in __pll_disable()
210 iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); in __pll_disable()
220 val = readl(pll->control_base + ctrl->aon.offset); in __pll_enable()
221 val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); in __pll_enable()
[all …]
Dclk-bcm281xx.c39 /* AON CCU */
69 BCM281XX_CCU_COMMON(aon, AON),
72 KONA_CLK(aon, hub_timer, peri),
74 KONA_CLK(aon, pmu_bsc, peri),
76 KONA_CLK(aon, pmu_bsc_var, peri),
Dclk-sr.c37 .aon = AON_VAL(0x0, 5, 1, 0),
97 .aon = AON_VAL(0x0, 1, 13, 12),
156 .aon = AON_VAL(0x0, 1, 19, 18),
191 .aon = AON_VAL(0x0, 1, 25, 24),
245 .aon = AON_VAL(0x0, 1, 1, 0),
283 .aon = AON_VAL(0x0, 2, 19, 18),
328 .aon = AON_VAL(0x0, 2, 22, 21),
367 .aon = AON_VAL(0x0, 2, 25, 24),
/kernel/linux/linux-6.6/drivers/clk/bcm/
Dclk-iproc-pll.c187 val = readl(pll->control_base + ctrl->aon.offset); in __pll_disable()
188 val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift; in __pll_disable()
189 iproc_pll_write(pll, pll->control_base, ctrl->aon.offset, val); in __pll_disable()
194 val = readl(pll->pwr_base + ctrl->aon.offset); in __pll_disable()
195 val |= 1 << ctrl->aon.iso_shift; in __pll_disable()
196 iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); in __pll_disable()
199 val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); in __pll_disable()
200 iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); in __pll_disable()
210 val = readl(pll->control_base + ctrl->aon.offset); in __pll_enable()
211 val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); in __pll_enable()
[all …]
Dclk-bcm281xx.c31 /* AON CCU */
61 BCM281XX_CCU_COMMON(aon, AON),
64 KONA_CLK(aon, hub_timer, peri),
66 KONA_CLK(aon, pmu_bsc, peri),
68 KONA_CLK(aon, pmu_bsc_var, peri),
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/gpio/
Dnvidia,tegra186-gpio.txt3 Tegra186 contains two GPIO controllers; a main controller and an "AON"
70 - "nvidia,tegra186-gpio-aon".
72 - "nvidia,tegra194-gpio-aon".
95 - "nvidia,tegra186-gpio-aon": 1 entry.
97 - "nvidia,tegra194-gpio-aon": 1 entry.
154 compatible = "nvidia,tegra186-gpio-aon";
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/starfive/
Dstarfive,jh7110-syscon.yaml25 - starfive,jh7110-aon-syscon
59 const: starfive,jh7110-aon-syscon
88 compatible = "starfive,jh7110-aon-syscon", "syscon";
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/
Dpinctrl-zx.txt28 | AGPIO10 ---+------ KEY_ROW2 (AON pin)
40 the pin spread in both controllers. This type of pins are called 'AON pins'.
49 implements pinmux for AON pins and pinconf for all pins.
/kernel/linux/linux-6.6/drivers/pinctrl/starfive/
Dpinctrl-starfive-jh7110-aon.c3 * Pinctrl / GPIO driver for StarFive JH7110 SoC aon controller
159 .compatible = "starfive,jh7110-aon-pinctrl",
169 .name = "starfive-jh7110-aon-pinctrl",
176 MODULE_DESCRIPTION("Pinctrl driver for the StarFive JH7110 SoC aon controller");
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/bcm/
Dbrcm,brcmstb.txt128 = Always-On control block (AON CTRL)
134 - compatible : should contain "brcm,brcmstb-aon-ctrl"
135 - reg : the register start and length for the AON CTRL block
139 aon-ctrl@410000 {
140 compatible = "brcm,brcmstb-aon-ctrl";
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/bcm/
Dbrcm,brcmstb.txt128 = Always-On control block (AON CTRL)
134 - compatible : should contain "brcm,brcmstb-aon-ctrl"
135 - reg : the register start and length for the AON CTRL block
139 aon-ctrl@410000 {
140 compatible = "brcm,brcmstb-aon-ctrl";

1234567