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/kernel/linux/linux-5.10/Documentation/arm64/
Damu.rst9 Date: 2019-09-10
16 ---------------------
24 optional external memory-mapped interface.
27 of four fixed and architecturally defined 64-bit event counters.
29 - CPU cycle counter: increments at the frequency of the CPU.
30 - Constant counter: increments at the fixed frequency of the system
32 - Instructions retired: increments with every architecturally executed
34 - Memory stall cycles: counts instruction dispatch stall cycles caused by
44 64-bit event counters.
50 -------------
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/kernel/linux/linux-6.6/Documentation/arch/arm64/
Damu.rst9 Date: 2019-09-10
16 ---------------------
24 optional external memory-mapped interface.
27 of four fixed and architecturally defined 64-bit event counters.
29 - CPU cycle counter: increments at the frequency of the CPU.
30 - Constant counter: increments at the fixed frequency of the system
32 - Instructions retired: increments with every architecturally executed
34 - Memory stall cycles: counts instruction dispatch stall cycles caused by
44 64-bit event counters.
50 -------------
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/
Darm,coresight-cti.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/arm,coresight-cti.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
21 number is defined at design time, the maximum of each defined in the DEVID
25 programmable channels, usually 4, but again implementation defined and
31 are implementation defined, except when the CTI is connected to an ARM v8
36 architecturally connected CTI an additional compatible string is used to
37 indicate this feature (arm,coresight-cti-v8-arch).
51 and usages. These can be defined along with the signal indexes with the
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/
Dcoresight-cti.yaml1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/coresight-cti.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
22 number is defined at design time, the maximum of each defined in the DEVID
26 programmable channels, usually 4, but again implementation defined and
32 are implementation defined, except when the CTI is connected to an ARM v8
37 architecturally connected CTI an additional compatible string is used to
38 indicate this feature (arm,coresight-cti-v8-arch).
52 and usages. These can be defined along with the signal indexes with the
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/
Driscv,cpu-intc.txt1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
20 interrupt map is defined by the ISA it's not listed in the HLIC's device tree
27 - compatible : "riscv,cpu-intc"
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Driscv,cpu-intc.txt1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
20 interrupt map is defined by the ISA it's not listed in the HLIC's device tree
27 - compatible : "riscv,cpu-intc"
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/kernel/linux/linux-6.6/arch/arm/include/asm/
Dvirt.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
14 * architecturally defined flag bit here.
24 * A correctly-implemented bootloader must start all CPUs in the same mode:
/kernel/linux/linux-5.10/arch/arm/include/asm/
Dvirt.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
14 * architecturally defined flag bit here.
24 * A correctly-implemented bootloader must start all CPUs in the same mode:
/kernel/linux/linux-5.10/Documentation/virt/kvm/devices/
Darm-vgic-v3.rst1 .. SPDX-License-Identifier: GPL-2.0
9 - KVM_DEV_TYPE_ARM_VGIC_V3 ARM Generic Interrupt Controller v3.0
12 will act as the VM interrupt controller, requiring emulated user-space devices
23 KVM_VGIC_V3_ADDR_TYPE_DIST (rw, 64-bit)
28 KVM_VGIC_V3_ADDR_TYPE_REDIST (rw, 64-bit)
35 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION (rw, 64-bit)
38 bits: | 63 .... 52 | 51 .... 16 | 15 - 12 |11 - 0
41 - index encodes the unique redistributor region index
42 - flags: reserved for future use, currently 0
43 - base field encodes bits [51:16] of the guest physical base address
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/kernel/linux/linux-6.6/Documentation/virt/kvm/devices/
Darm-vgic-v3.rst1 .. SPDX-License-Identifier: GPL-2.0
9 - KVM_DEV_TYPE_ARM_VGIC_V3 ARM Generic Interrupt Controller v3.0
12 will act as the VM interrupt controller, requiring emulated user-space devices
23 KVM_VGIC_V3_ADDR_TYPE_DIST (rw, 64-bit)
28 KVM_VGIC_V3_ADDR_TYPE_REDIST (rw, 64-bit)
35 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION (rw, 64-bit)
38 bits: | 63 .... 52 | 51 .... 16 | 15 - 12 |11 - 0
41 - index encodes the unique redistributor region index
42 - flags: reserved for future use, currently 0
43 - base field encodes bits [51:16] of the guest physical base address
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/
Darm,arch_timer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
17 The per-core architected timer is attached to a GIC to deliver its
18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
24 - items:
25 - enum:
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Darm,arch_timer_mmio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
22 - enum:
23 - arm,armv7-timer-mem
29 '#address-cells':
32 '#size-cells':
37 clock-frequency:
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/timer/
Darm,arch_timer_mmio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
22 - enum:
23 - arm,armv7-timer-mem
29 '#address-cells':
32 '#size-cells':
37 clock-frequency:
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Darm,arch_timer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
17 The per-core architected timer is attached to a GIC to deliver its
18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
24 - items:
25 - const: arm,cortex-a15-timer
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/kernel/linux/linux-6.6/arch/parisc/kernel/
Dvmlinux.lds.S1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright (C) 1999-2003 Matthew Wilcox <willy at parisc-linux.org>
5 * Copyright (C) 2000-2003 Paul Bame <bame at parisc-linux.org>
6 * Copyright (C) 2000 John Marvin <jsm at parisc-linux.org>
8 * Copyright (C) 2002 Randolph Chung <tausq with parisc-linux.org>
9 * Copyright (C) 2003 James Bottomley <jejb with parisc-linux.org>
10 * Copyright (C) 2006-2013 Helge Deller <deller@gmx.de>
24 #include <asm-generic/vmlinux.lds.h>
29 #include <asm/asm-offsets.h>
34 OUTPUT_FORMAT("elf32-hppa-linux")
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/kernel/linux/linux-5.10/arch/parisc/kernel/
Dvmlinux.lds.S1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright (C) 1999-2003 Matthew Wilcox <willy at parisc-linux.org>
5 * Copyright (C) 2000-2003 Paul Bame <bame at parisc-linux.org>
6 * Copyright (C) 2000 John Marvin <jsm at parisc-linux.org>
8 * Copyright (C) 2002 Randolph Chung <tausq with parisc-linux.org>
9 * Copyright (C) 2003 James Bottomley <jejb with parisc-linux.org>
10 * Copyright (C) 2006-2013 Helge Deller <deller@gmx.de>
24 #include <asm-generic/vmlinux.lds.h>
29 #include <asm/asm-offsets.h>
34 OUTPUT_FORMAT("elf32-hppa-linux")
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/kernel/linux/linux-5.10/Documentation/x86/
Dentry_64.rst1 .. SPDX-License-Identifier: GPL-2.0
16 for 64-bit, arch/x86/entry/entry_32.S for 32-bit and finally
17 arch/x86/entry/entry_64_compat.S which implements the 32-bit compatibility
18 syscall entry points and thus provides for 32-bit processes the
19 ability to execute syscalls when running on 64-bit kernels.
25 - system_call: syscall instruction from 64-bit code.
27 - entry_INT80_compat: int 0x80 from 32-bit or 64-bit code; compat syscall
30 - entry_INT80_compat, ia32_sysenter: syscall and sysenter from 32-bit
33 - interrupt: An array of entries. Every IDT vector that doesn't
36 magically-generated functions that make their way to do_IRQ with
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/kernel/linux/linux-6.6/Documentation/arch/x86/
Dentry_64.rst1 .. SPDX-License-Identifier: GPL-2.0
16 for 64-bit, arch/x86/entry/entry_32.S for 32-bit and finally
17 arch/x86/entry/entry_64_compat.S which implements the 32-bit compatibility
18 syscall entry points and thus provides for 32-bit processes the
19 ability to execute syscalls when running on 64-bit kernels.
25 - system_call: syscall instruction from 64-bit code.
27 - entry_INT80_compat: int 0x80 from 32-bit or 64-bit code; compat syscall
30 - entry_INT80_compat, ia32_sysenter: syscall and sysenter from 32-bit
33 - interrupt: An array of entries. Every IDT vector that doesn't
36 magically-generated functions that make their way to common_interrupt()
[all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/silvermont/
Dpipeline.json96 …architecturally defined event. This event counts the number of retired branch instructions that we…
104 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
113 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
122 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
131 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
140 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
147 …by dividing the event count by the core frequency. This event is architecturally defined and is a …
169 …lapsed time while the core was not in halt state. This event is architecturally defined and is a …
184 … For instructions that consist of multiple micro-ops, this event counts exactly once, as the last …
192 … For instructions that consist of multiple micro-ops, this event counts the retirement of the last…
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/kernel/linux/linux-5.10/drivers/hwtracing/coresight/
Dcoresight-cti-platform.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <dt-bindings/arm/coresight-cti-dt.h>
14 #include "coresight-cti.h"
15 #include "coresight-priv.h"
17 /* Number of CTI signals in the v8 architecturally defined connection */
23 #define CTI_DT_CONNS "trig-conns"
26 #define CTI_DT_V8ARCH_COMPAT "arm,coresight-cti-v8-arch"
27 #define CTI_DT_CSDEV_ASSOC "arm,cs-dev-assoc"
28 #define CTI_DT_TRIGIN_SIGS "arm,trig-in-sigs"
29 #define CTI_DT_TRIGOUT_SIGS "arm,trig-out-sigs"
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/kernel/linux/linux-6.6/drivers/hwtracing/coresight/
Dcoresight-cti-platform.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <dt-bindings/arm/coresight-cti-dt.h>
14 #include "coresight-cti.h"
15 #include "coresight-priv.h"
17 /* Number of CTI signals in the v8 architecturally defined connection */
23 #define CTI_DT_CONNS "trig-conns"
26 #define CTI_DT_V8ARCH_COMPAT "arm,coresight-cti-v8-arch"
27 #define CTI_DT_CSDEV_ASSOC "arm,cs-dev-assoc"
28 #define CTI_DT_TRIGIN_SIGS "arm,trig-in-sigs"
29 #define CTI_DT_TRIGOUT_SIGS "arm,trig-out-sigs"
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/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/silvermont/
Dpipeline.json94 …architecturally defined event. This event counts the number of retired branch instructions that we…
104 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
114 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
124 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
134 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
144 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
153 …"PublicDescription": "This event counts the number of micro-ops retired that were supplied from MS…
159 "BriefDescription": "MSROM micro-ops retired"
162 …-ops retired. The processor decodes complex macro instructions into a sequence of simpler micro-op…
168 "BriefDescription": "Micro-ops retired"
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/kernel/linux/linux-5.10/Documentation/trace/coresight/
Dcoresight-ect.rst1 .. SPDX-License-Identifier: GPL-2.0
11 --------------------
21 0 C 0----------->: : +======>(other CTI channel IO)
22 0 P 0<-----------: : v
24 0000000 : CTI :<=========>*CTM*<====>: CTI :---+
25 ####### in_trigs : : (id 0-3) ***** ::::::: v
26 # ETM #----------->: : ^ #######
27 # #<-----------: : +---# ETR #
47 defined, unless the CPU/ETM combination is a v8 architecture, in which case
48 the connections have an architecturally defined standard layout.
[all …]
/kernel/linux/linux-6.6/Documentation/trace/coresight/
Dcoresight-ect.rst1 .. SPDX-License-Identifier: GPL-2.0
11 --------------------
21 0 C 0----------->: : +======>(other CTI channel IO)
22 0 P 0<-----------: : v
24 0000000 : CTI :<=========>*CTM*<====>: CTI :---+
25 ####### in_trigs : : (id 0-3) ***** ::::::: v
26 # ETM #----------->: : ^ #######
27 # #<-----------: : +---# ETR #
47 defined, unless the CPU/ETM combination is a v8 architecture, in which case
48 the connections have an architecturally defined standard layout.
[all …]
/kernel/linux/linux-6.6/arch/x86/lib/
Dretpoline.S1 /* SPDX-License-Identifier: GPL-2.0 */
8 #include <asm/asm-offsets.h>
10 #include <asm/nospec-branch.h>
64 #include <asm/GEN-for-each-reg.h>
71 #include <asm/GEN-for-each-reg.h>
93 #include <asm/GEN-for-each-reg.h>
100 #include <asm/GEN-for-each-reg.h>
119 #include <asm/GEN-for-each-reg.h>
126 #include <asm/GEN-for-each-reg.h>
140 * - srso_alias_untrain_ret() is 2M aligned
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