Home
last modified time | relevance | path

Searched +full:aspm +full:- +full:no +full:- +full:l0s (Results 1 – 25 of 46) sorted by relevance

12

/kernel/linux/linux-5.10/drivers/pci/pcie/
Daspm.c1 // SPDX-License-Identifier: GPL-2.0
3 * Enable PCIe link L0s/L1 state and Clock Power Management
29 #define ASPM_STATE_L0S_UP (1) /* Upstream direction L0s state */
30 #define ASPM_STATE_L0S_DW (2) /* Downstream direction L0s state */
32 #define ASPM_STATE_L1_1 (8) /* ASPM L1.1 state */
33 #define ASPM_STATE_L1_2 (0x10) /* ASPM L1.2 state */
45 u32 l0s; /* L0s latency (nsec) */ member
56 /* ASPM state */
57 u32 aspm_support:7; /* Supported ASPM state */
58 u32 aspm_enabled:7; /* Enabled ASPM state */
[all …]
/kernel/linux/linux-6.6/drivers/pci/pcie/
Daspm.c1 // SPDX-License-Identifier: GPL-2.0
3 * Enable PCIe link L0s/L1 state and Clock Power Management
30 #define ASPM_STATE_L0S_UP (1) /* Upstream direction L0s state */
31 #define ASPM_STATE_L0S_DW (2) /* Downstream direction L0s state */
33 #define ASPM_STATE_L1_1 (8) /* ASPM L1.1 state */
34 #define ASPM_STATE_L1_2 (0x10) /* ASPM L1.2 state */
52 /* ASPM state */
53 u32 aspm_support:7; /* Supported ASPM state */
54 u32 aspm_enabled:7; /* Enabled ASPM state */
55 u32 aspm_capable:7; /* Capable ASPM state with latency */
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/
Dnvidia,tegra194-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
16 inherits all the common properties defined in snps,dw-pcie-ep.yaml. Some
23 Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
29 - nvidia,tegra194-pcie-ep
[all …]
Dnvidia,tegra194-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
20 See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device
26 - nvidia,tegra194-pcie
[all …]
Drockchip,rk3399-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Lin <shawn.lin@rock-chips.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
18 const: rockchip,rk3399-pcie
22 reg-names:
24 - const: axi-base
[all …]
Dbrcm,stb-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
15 - enum:
16 - brcm,bcm2711-pcie # The Raspberry Pi 4
17 - brcm,bcm4908-pcie
18 - brcm,bcm7211-pcie # Broadcom STB version of RPi4
19 - brcm,bcm7278-pcie # Broadcom 7278 Arm
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/
Drockchip-pcie-host.txt4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
8 - compatible: Should contain "rockchip,rk3399-pcie"
9 - reg: Two register ranges as listed in the reg-names property
10 - reg-names: Must include the following names
11 - "axi-base"
12 - "apb-base"
13 - clocks: Must contain an entry for each entry in clock-names.
14 See ../clocks/clock-bindings.txt for details.
[all …]
Dbrcm,stb-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
15 - enum:
16 - brcm,bcm2711-pcie # The Raspberry Pi 4
17 - brcm,bcm7211-pcie # Broadcom STB version of RPi4
18 - brcm,bcm7278-pcie # Broadcom 7278 Arm
19 - brcm,bcm7216-pcie # Broadcom 7216 Arm
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/nvidia/
Dtegra234.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
9 #include <dt-bindings/power/tegra234-powergate.h>
10 #include <dt-bindings/reset/tegra234-reset.h>
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
[all …]
Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
[all …]
/kernel/linux/linux-5.10/drivers/pci/controller/dwc/
Dpcie-tegra194.c1 // SPDX-License-Identifier: GPL-2.0+
34 #include "pcie-designware.h"
36 #include <soc/tegra/bpmp-abi.h>
324 writel_relaxed(value, pcie->appl_base + reg); in appl_writel()
329 return readl_relaxed(pcie->appl_base + reg); in appl_readl()
344 * NOTE:- Since this scenario is uncommon and link as such is not in apply_bad_link_workaround()
346 * transitioning to Gen-2 speed in apply_bad_link_workaround()
348 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in apply_bad_link_workaround()
351 if (pcie->init_link_width > current_link_width) { in apply_bad_link_workaround()
352 dev_warn(pci->dev, "PCIe link is bad, width reduced\n"); in apply_bad_link_workaround()
[all …]
/kernel/linux/linux-6.6/drivers/pci/controller/dwc/
Dpcie-tegra194.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Copyright (C) 2019-2022 NVIDIA Corporation.
35 #include "pcie-designware.h"
37 #include <soc/tegra/bpmp-abi.h>
303 writel_relaxed(value, pcie->appl_base + reg); in appl_writel()
308 return readl_relaxed(pcie->appl_base + reg); in appl_readl()
317 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_icc_set()
320 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in tegra_pcie_icc_set()
327 if (icc_set_bw(pcie->icc_path, MBps_to_icc(val), 0)) in tegra_pcie_icc_set()
328 dev_err(pcie->dev, "can't set bw[%u]\n", val); in tegra_pcie_icc_set()
[all …]
/kernel/linux/linux-6.6/include/uapi/linux/
Dpci_regs.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
5 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
25 * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
26 * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of
50 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
59 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
123 /* 0x35-0x3b are reserved */
129 /* Header type 1 (PCI-to-PCI bridges) */
157 /* 0x35-0x3b is reserved */
159 /* 0x3c-0x3d are same as for htype 0 */
[all …]
/kernel/linux/linux-5.10/include/uapi/linux/
Dpci_regs.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
5 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
25 * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
26 * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of
50 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
59 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
123 /* 0x35-0x3b are reserved */
129 /* Header type 1 (PCI-to-PCI bridges) */
157 /* 0x35-0x3b is reserved */
159 /* 0x3c-0x3d are same as for htype 0 */
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
Dnbio_v2_3.c16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
70 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); in nbio_v2_3_remap_hdp_registers()
72 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); in nbio_v2_3_remap_hdp_registers()
177 lower_32_bits(adev->doorbell.base)); in nbio_v2_3_enable_doorbell_selfring_aperture()
179 upper_32_bits(adev->doorbell.base)); in nbio_v2_3_enable_doorbell_selfring_aperture()
212 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); in nbio_v2_3_ih_control()
216 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi in nbio_v2_3_ih_control()
217 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN in nbio_v2_3_ih_control()
222 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ in nbio_v2_3_ih_control()
234 if (!(adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) in nbio_v2_3_update_medium_grain_clock_gating()
[all …]
/kernel/linux/linux-5.10/drivers/pci/controller/
Dpcie-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
34 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
175 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX])
176 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA])
177 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1])
267 int nr; /* No. of MSI available, depends on chip */
294 * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
302 return (log2_in - 12) + 0x1c; in brcm_pcie_encode_ibar_size()
305 return log2_in - 15; in brcm_pcie_encode_ibar_size()
[all …]
Dpcie-rockchip-host.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Wenrui Li <wenrui.li@rock-chips.com>
40 #include "pcie-rockchip.h"
79 if (pci_is_root_bus(bus) || pci_is_root_bus(bus->parent)) in rockchip_pcie_valid_device()
90 if (rockchip->legacy_phy) in rockchip_pcie_lane_map()
91 return GENMASK(MAX_LANE_NUM - 1, 0); in rockchip_pcie_lane_map()
96 /* The link may be using a reverse-indexed mapping. */ in rockchip_pcie_lane_map()
108 addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + where; in rockchip_pcie_rd_own_conf()
135 addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + offset; in rockchip_pcie_wr_own_conf()
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/ath/ath9k/
Dar9002_hw.c2 * Copyright (c) 2008-2011 Atheros Communications Inc.
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
29 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271); in ar9002_hw_init_mode_regs()
30 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271); in ar9002_hw_init_mode_regs()
31 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg); in ar9002_hw_init_mode_regs()
35 INIT_INI_ARRAY(&ah->iniPcieSerdes, in ar9002_hw_init_mode_regs()
39 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1); in ar9002_hw_init_mode_regs()
40 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1); in ar9002_hw_init_mode_regs()
42 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2); in ar9002_hw_init_mode_regs()
43 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2); in ar9002_hw_init_mode_regs()
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/ath/ath9k/
Dar9002_hw.c2 * Copyright (c) 2008-2011 Atheros Communications Inc.
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
29 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271); in ar9002_hw_init_mode_regs()
30 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271); in ar9002_hw_init_mode_regs()
31 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg); in ar9002_hw_init_mode_regs()
35 INIT_INI_ARRAY(&ah->iniPcieSerdes, in ar9002_hw_init_mode_regs()
39 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1); in ar9002_hw_init_mode_regs()
40 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1); in ar9002_hw_init_mode_regs()
42 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2); in ar9002_hw_init_mode_regs()
43 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2); in ar9002_hw_init_mode_regs()
[all …]
/kernel/linux/linux-6.6/drivers/pci/controller/
Dpcie-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
26 #include <linux/pci-ecam.h>
37 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
152 #define BRCM_INT_PCI_MSI_MASK GENMASK(BRCM_INT_PCI_MSI_NR - 1, 0)
154 32 - BRCM_INT_PCI_MSI_LEGACY_NR)
181 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX])
182 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA])
183 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1])
243 int nr; /* No. of MSI available, depends on chip */
[all …]
Dpcie-rockchip-host.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Wenrui Li <wenrui.li@rock-chips.com>
37 #include "pcie-rockchip.h"
76 if (pci_is_root_bus(bus) || pci_is_root_bus(bus->parent)) in rockchip_pcie_valid_device()
87 if (rockchip->legacy_phy) in rockchip_pcie_lane_map()
88 return GENMASK(MAX_LANE_NUM - 1, 0); in rockchip_pcie_lane_map()
93 /* The link may be using a reverse-indexed mapping. */ in rockchip_pcie_lane_map()
105 addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + where; in rockchip_pcie_rd_own_conf()
132 addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + offset; in rockchip_pcie_wr_own_conf()
[all …]
/kernel/linux/linux-6.6/arch/mips/boot/dts/brcm/
Dbcm7435.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <175625000>;
42 cpu_intc: interrupt-controller {
43 #address-cells = <0>;
44 compatible = "mti,cpu-interrupt-controller";
46 interrupt-controller;
[all …]
Dbcm7425.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <163125000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
[all …]
/kernel/linux/linux-6.6/arch/sh/drivers/pci/
Dpcie-sh7786.c1 // SPDX-License-Identifier: GPL-2.0
3 * Low-Level PCI Express Support for the SH7786
5 * Copyright (C) 2009 - 2011 Paul Mundt
15 #include <linux/dma-map-ops.h>
21 #include "pcie-sh7786.h"
46 .end = 0xfd000000 + SZ_8M - 1,
51 .end = 0xc0000000 + SZ_512M - 1,
56 .end = 0x10000000 + SZ_64M - 1,
61 .end = 0xfe100000 + SZ_1M - 1,
70 .end = 0xfd800000 + SZ_8M - 1,
[all …]
/kernel/linux/linux-5.10/arch/sh/drivers/pci/
Dpcie-sh7786.c1 // SPDX-License-Identifier: GPL-2.0
3 * Low-Level PCI Express Support for the SH7786
5 * Copyright (C) 2009 - 2011 Paul Mundt
15 #include <linux/dma-mapping.h>
21 #include "pcie-sh7786.h"
47 .end = 0xfd000000 + SZ_8M - 1,
52 .end = 0xc0000000 + SZ_512M - 1,
57 .end = 0x10000000 + SZ_64M - 1,
62 .end = 0xfe100000 + SZ_1M - 1,
71 .end = 0xfd800000 + SZ_8M - 1,
[all …]

12