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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/
Dnvidia,tegra194-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
15 This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
16 inherits all the common properties defined in snps,dw-pcie-ep.yaml. Some
20 On Tegra194, controllers C0, C4 and C5 support Endpoint mode.
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Dnvidia,tegra194-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
15 This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
20 See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/
Dnvidia,tegra194-pcie.txt3 This PCIe controller is based on the Synopsis Designware PCIe IP
4 and thus inherits all the common properties defined in designware-pcie.txt.
9 - power-domains: A phandle to the node that controls power to the respective
19 "include/dt-bindings/power/tegra194-powergate.h" file.
20 - reg: A list of physical base address and length pairs for each set of
21 controller registers. Must contain an entry for each entry in the reg-names
23 - reg-names: Must include the following entries:
25 "config": As per the definition in designware-pcie.txt
31 - interrupts: A list of interrupt outputs of the controller. Must contain an
32 entry for each entry in the interrupt-names property.
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/nvidia/
Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
7 #include <dt-bindings/power/tegra194-powergate.h>
8 #include <dt-bindings/reset/tegra194-reset.h>
9 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
10 #include <dt-bindings/memory/tegra194-mc.h>
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/kernel/linux/linux-6.6/arch/arm64/boot/dts/nvidia/
Dtegra234.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
9 #include <dt-bindings/power/tegra234-powergate.h>
10 #include <dt-bindings/reset/tegra234-reset.h>
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
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Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
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/kernel/linux/linux-5.10/drivers/pci/controller/dwc/
Dpcie-tegra194.c1 // SPDX-License-Identifier: GPL-2.0+
34 #include "pcie-designware.h"
36 #include <soc/tegra/bpmp-abi.h>
324 writel_relaxed(value, pcie->appl_base + reg); in appl_writel()
329 return readl_relaxed(pcie->appl_base + reg); in appl_readl()
344 * NOTE:- Since this scenario is uncommon and link as such is not in apply_bad_link_workaround()
346 * transitioning to Gen-2 speed in apply_bad_link_workaround()
348 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in apply_bad_link_workaround()
351 if (pcie->init_link_width > current_link_width) { in apply_bad_link_workaround()
352 dev_warn(pci->dev, "PCIe link is bad, width reduced\n"); in apply_bad_link_workaround()
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/kernel/linux/linux-6.6/drivers/pci/controller/dwc/
Dpcie-tegra194.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Copyright (C) 2019-2022 NVIDIA Corporation.
35 #include "pcie-designware.h"
37 #include <soc/tegra/bpmp-abi.h>
303 writel_relaxed(value, pcie->appl_base + reg); in appl_writel()
308 return readl_relaxed(pcie->appl_base + reg); in appl_readl()
317 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_icc_set()
320 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in tegra_pcie_icc_set()
327 if (icc_set_bw(pcie->icc_path, MBps_to_icc(val), 0)) in tegra_pcie_icc_set()
328 dev_err(pcie->dev, "can't set bw[%u]\n", val); in tegra_pcie_icc_set()
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/kernel/linux/linux-6.6/drivers/net/wireless/broadcom/b43/
Db43.h1 /* SPDX-License-Identifier: GPL-2.0 */
61 /* 32-bit DMA */
68 /* 64-bit DMA */
76 /* PIO on core rev < 11 */
85 /* PIO on core rev >= 11 */
203 #define B43_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
207 #define B43_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */
209 #define B43_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
211 #define B43_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
212 #define B43_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
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/kernel/linux/linux-5.10/drivers/net/wireless/broadcom/b43/
Db43.h1 /* SPDX-License-Identifier: GPL-2.0 */
61 /* 32-bit DMA */
68 /* 64-bit DMA */
76 /* PIO on core rev < 11 */
85 /* PIO on core rev >= 11 */
203 #define B43_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
207 #define B43_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */
209 #define B43_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
211 #define B43_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
212 #define B43_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
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/kernel/linux/linux-6.6/drivers/net/wireless/realtek/rtlwifi/rtl8192de/
Dhw.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
48 rtlpci->reg_bcn_ctrl_val |= set_bits; in _rtl92de_set_bcn_ctrl_reg()
49 rtlpci->reg_bcn_ctrl_val &= ~clear_bits; in _rtl92de_set_bcn_ctrl_reg()
50 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val); in _rtl92de_set_bcn_ctrl_reg()
99 *((u32 *) (val)) = rtlpci->receive_config; in rtl92de_get_hw_reg()
102 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; in rtl92de_get_hw_reg()
108 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, in rtl92de_get_hw_reg()
123 *((bool *) (val)) = ppsc->fw_current_inpsmode; in rtl92de_get_hw_reg()
136 *((bool *)(val)) = rtlpriv->dm.interrupt_migration; in rtl92de_get_hw_reg()
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/kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtlwifi/rtl8192de/
Dhw.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
48 rtlpci->reg_bcn_ctrl_val |= set_bits; in _rtl92de_set_bcn_ctrl_reg()
49 rtlpci->reg_bcn_ctrl_val &= ~clear_bits; in _rtl92de_set_bcn_ctrl_reg()
50 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val); in _rtl92de_set_bcn_ctrl_reg()
99 *((u32 *) (val)) = rtlpci->receive_config; in rtl92de_get_hw_reg()
102 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; in rtl92de_get_hw_reg()
108 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, in rtl92de_get_hw_reg()
123 *((bool *) (val)) = ppsc->fw_current_inpsmode; in rtl92de_get_hw_reg()
136 *((bool *)(val)) = rtlpriv->dm.interrupt_migration; in rtl92de_get_hw_reg()
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/kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
Dhw.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
27 *((u32 *) (val)) = rtlpci->receive_config; in rtl92se_get_hw_reg()
31 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; in rtl92se_get_hw_reg()
35 *((bool *) (val)) = ppsc->fw_current_inpsmode; in rtl92se_get_hw_reg()
51 *((bool *)(val)) = rtlpriv->dm.current_mrc_switch; in rtl92se_get_hw_reg()
81 if (rtlhal->version == VERSION_8192S_ACUT) in rtl92se_set_hw_reg()
120 rtlpriv->cfg->ops->set_hw_reg(hw, in rtl92se_set_hw_reg()
129 reg_tmp = (mac->cur_40_prime_sc) << 5; in rtl92se_set_hw_reg()
142 if (rtlpriv->sec.pairwise_enc_algorithm == in rtl92se_set_hw_reg()
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/kernel/linux/linux-6.6/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
Dhw.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
27 *((u32 *) (val)) = rtlpci->receive_config; in rtl92se_get_hw_reg()
31 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; in rtl92se_get_hw_reg()
35 *((bool *) (val)) = ppsc->fw_current_inpsmode; in rtl92se_get_hw_reg()
51 *((bool *)(val)) = rtlpriv->dm.current_mrc_switch; in rtl92se_get_hw_reg()
81 if (rtlhal->version == VERSION_8192S_ACUT) in rtl92se_set_hw_reg()
120 rtlpriv->cfg->ops->set_hw_reg(hw, in rtl92se_set_hw_reg()
129 reg_tmp = (mac->cur_40_prime_sc) << 5; in rtl92se_set_hw_reg()
142 if (rtlpriv->sec.pairwise_enc_algorithm == in rtl92se_set_hw_reg()
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/kernel/linux/patches/linux-5.10/imx8mm_patch/patches/drivers/
D0030_linux_drivers_pci_misc_nvmem_of_mtd_mmc.patch7 Change-Id: Iec160bd007994d82f416debdccfbc0d9bdb40470
9 diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
11 --- a/drivers/misc/Kconfig
13 @@ -314,6 +314,26 @@ config ISL29020
19 + depends on I2C && SYSFS
29 + depends on I2C && SYSFS
39 depends on I2C && SYSFS
40 diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
42 --- a/drivers/misc/Makefile
44 @@ -19,6 +19,8 @@ obj-$(CONFIG_TIFM_7XX1) += tifm_7xx1.o
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