Home
last modified time | relevance | path

Searched +full:assigned +full:- +full:addresses (Results 1 – 25 of 769) sorted by relevance

12345678910>>...31

/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/
Dmvebu-pci.txt5 - compatible: one of the following values:
6 marvell,armada-370-pcie
7 marvell,armada-xp-pcie
8 marvell,dove-pcie
9 marvell,kirkwood-pcie
10 - #address-cells, set to <3>
11 - #size-cells, set to <2>
12 - #interrupt-cells, set to <1>
13 - bus-range: PCI bus numbers covered
14 - device_type, set to "pci"
[all …]
Dnvidia,tegra20-pcie.txt4 - compatible: Must be:
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
10 - power-domains: To ungate power partition by BPMP powergate driver. Must
13 - device_type: Must be "pci"
14 - reg: A list of physical base address and length for each set of controller
15 registers. Must contain an entry for each entry in the reg-names property.
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/
Dmvebu-pci.txt5 - compatible: one of the following values:
6 marvell,armada-370-pcie
7 marvell,armada-xp-pcie
8 marvell,dove-pcie
9 marvell,kirkwood-pcie
10 - #address-cells, set to <3>
11 - #size-cells, set to <2>
12 - #interrupt-cells, set to <1>
13 - bus-range: PCI bus numbers covered
14 - device_type, set to "pci"
[all …]
Dnvidia,tegra20-pcie.txt4 - compatible: Must be:
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
10 - power-domains: To ungate power partition by BPMP powergate driver. Must
13 - device_type: Must be "pci"
14 - reg: A list of physical base address and length for each set of controller
15 registers. Must contain an entry for each entry in the reg-names property.
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Darmada-xp-mv78260.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
26 #address-cells = <1>;
27 #size-cells = <0>;
28 enable-method = "marvell,armada-xp-smp";
32 compatible = "marvell,sheeva-v7";
35 clock-latency = <1000000>;
40 compatible = "marvell,sheeva-v7";
[all …]
Darmada-xp-mv78460.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,armada-xp-smp";
33 compatible = "marvell,sheeva-v7";
36 clock-latency = <1000000>;
41 compatible = "marvell,sheeva-v7";
[all …]
Darmada-xp-mv78230.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
25 #address-cells = <1>;
26 #size-cells = <0>;
27 enable-method = "marvell,armada-xp-smp";
31 compatible = "marvell,sheeva-v7";
34 clock-latency = <1000000>;
39 compatible = "marvell,sheeva-v7";
[all …]
Darmada-385.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include "armada-38x.dtsi"
19 #address-cells = <1>;
20 #size-cells = <0>;
21 enable-method = "marvell,armada-380-smp";
25 compatible = "arm,cortex-a9";
30 compatible = "arm,cortex-a9";
37 compatible = "marvell,armada-370-pcie";
[all …]
Darmada-380.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include "armada-38x.dtsi"
19 #address-cells = <1>;
20 #size-cells = <0>;
21 enable-method = "marvell,armada-380-smp";
25 compatible = "arm,cortex-a9";
31 internal-regs {
33 compatible = "marvell,mv88f6810-pinctrl";
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/marvell/
Darmada-xp-mv78460.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,armada-xp-smp";
33 compatible = "marvell,sheeva-v7";
36 clock-latency = <1000000>;
41 compatible = "marvell,sheeva-v7";
[all …]
Darmada-xp-mv78260.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
26 #address-cells = <1>;
27 #size-cells = <0>;
28 enable-method = "marvell,armada-xp-smp";
32 compatible = "marvell,sheeva-v7";
35 clock-latency = <1000000>;
40 compatible = "marvell,sheeva-v7";
[all …]
Darmada-385.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include "armada-38x.dtsi"
19 #address-cells = <1>;
20 #size-cells = <0>;
21 enable-method = "marvell,armada-380-smp";
25 compatible = "arm,cortex-a9";
30 compatible = "arm,cortex-a9";
37 compatible = "marvell,armada-370-pcie";
[all …]
Darmada-xp-mv78230.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
25 #address-cells = <1>;
26 #size-cells = <0>;
27 enable-method = "marvell,armada-xp-smp";
31 compatible = "marvell,sheeva-v7";
34 clock-latency = <1000000>;
39 compatible = "marvell,sheeva-v7";
[all …]
Darmada-380.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include "armada-38x.dtsi"
19 #address-cells = <1>;
20 #size-cells = <0>;
21 enable-method = "marvell,armada-380-smp";
25 compatible = "arm,cortex-a9";
31 internal-regs {
33 compatible = "marvell,mv88f6810-pinctrl";
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dcavium-mdio.txt4 - compatible: One of:
6 "cavium,octeon-3860-mdio": Compatibility with all cn3XXX, cn5XXX
9 "cavium,thunder-8890-mdio": Compatibility with all cn8XXX SOCs.
11 - reg: The base address of the MDIO bus controller register bank.
13 - #address-cells: Must be <1>.
15 - #size-cells: Must be <0>. MDIO addresses have no size component.
21 compatible = "cavium,octeon-3860-mdio";
22 #address-cells = <1>;
23 #size-cells = <0>;
26 ethernet-phy@0 {
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dcavium-mdio.txt4 - compatible: One of:
6 "cavium,octeon-3860-mdio": Compatibility with all cn3XXX, cn5XXX
9 "cavium,thunder-8890-mdio": Compatibility with all cn8XXX SOCs.
11 - reg: The base address of the MDIO bus controller register bank.
13 - #address-cells: Must be <1>.
15 - #size-cells: Must be <0>. MDIO addresses have no size component.
21 compatible = "cavium,octeon-3860-mdio";
22 #address-cells = <1>;
23 #size-cells = <0>;
26 ethernet-phy@0 {
[all …]
Drockchip-dwmac.txt6 - compatible: should be "rockchip,<name>-gamc"
7 "rockchip,px30-gmac": found on PX30 SoCs
8 "rockchip,rk3128-gmac": found on RK312x SoCs
9 "rockchip,rk3228-gmac": found on RK322x SoCs
10 "rockchip,rk3288-gmac": found on RK3288 SoCs
11 "rockchip,rk3328-gmac": found on RK3328 SoCs
12 "rockchip,rk3366-gmac": found on RK3366 SoCs
13 "rockchip,rk3368-gmac": found on RK3368 SoCs
14 "rockchip,rk3399-gmac": found on RK3399 SoCs
15 "rockchip,rv1108-gmac": found on RV1108 SoCs
[all …]
/kernel/linux/linux-6.6/Documentation/ABI/testing/
Dsysfs-driver-intel-m10-bmc1 What: /sys/bus/.../drivers/intel-m10-bmc/.../bmc_version
9 What: /sys/bus/.../drivers/intel-m10-bmc/.../bmcfw_version
17 What: /sys/bus/.../drivers/intel-m10-bmc/.../mac_address
22 of sequential MAC addresses assigned to the board
28 What: /sys/bus/.../drivers/intel-m10-bmc/.../mac_count
33 addresses assigned to the board managed by the Intel
/kernel/linux/linux-6.6/Documentation/security/
DSCTP.rst1 .. SPDX-License-Identifier: GPL-2.0
11 --------------
26 Passes the ``@asoc`` and ``@chunk->skb`` of the association INIT packet to the
30 @asoc - pointer to sctp association structure.
31 @skb - pointer to skbuff of association packet.
36 Passes one or more ipv4/ipv6 addresses to the security module for validation
42 @sk - Pointer to sock structure.
43 @optname - Name of the option to validate.
44 @address - One or more ipv4 / ipv6 addresses.
45 @addrlen - The total length of address(s). This is calculated on each
[all …]
/kernel/linux/linux-5.10/Documentation/security/
DSCTP.rst1 .. SPDX-License-Identifier: GPL-2.0
11 --------------
29 Passes the ``@ep`` and ``@chunk->skb`` of the association INIT packet to the
33 @ep - pointer to sctp endpoint structure.
34 @skb - pointer to skbuff of association packet.
39 Passes one or more ipv4/ipv6 addresses to the security module for validation
45 @sk - Pointer to sock structure.
46 @optname - Name of the option to validate.
47 @address - One or more ipv4 / ipv6 addresses.
48 @addrlen - The total length of address(s). This is calculated on each
[all …]
/kernel/linux/linux-6.6/include/linux/
Detherdevice.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
69 /* Reserved Ethernet Addresses per IEEE 802.1Q */
75 * is_link_local_ether_addr - Determine if given Ethernet address is link-local
76 * @addr: Pointer to a six-byte array containing the Ethernet address
98 * is_zero_ether_addr - Determine if give Ethernet address is all zeros.
99 * @addr: Pointer to a six-byte array containing the Ethernet address
117 * is_multicast_ether_addr - Determine if the Ethernet address is a multicast.
118 * @addr: Pointer to a six-byte array containing the Ethernet address
131 return 0x01 & (a >> ((sizeof(a) * 8) - 8)); in is_multicast_ether_addr()
151 * is_local_ether_addr - Determine if the Ethernet address is locally-assigned one (IEEE 802).
[all …]
/kernel/linux/linux-5.10/include/linux/
Detherdevice.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
62 /* Reserved Ethernet Addresses per IEEE 802.1Q */
68 * is_link_local_ether_addr - Determine if given Ethernet address is link-local
69 * @addr: Pointer to a six-byte array containing the Ethernet address
91 * is_zero_ether_addr - Determine if give Ethernet address is all zeros.
92 * @addr: Pointer to a six-byte array containing the Ethernet address
110 * is_multicast_ether_addr - Determine if the Ethernet address is a multicast.
111 * @addr: Pointer to a six-byte array containing the Ethernet address
124 return 0x01 & (a >> ((sizeof(a) * 8) - 8)); in is_multicast_ether_addr()
144 * is_local_ether_addr - Determine if the Ethernet address is locally-assigned one (IEEE 802).
[all …]
/kernel/linux/linux-5.10/Documentation/powerpc/
Dpci_iov_resource_on_powernv.rst57 - For DMA we then provide an entire address space for each PE that can
63 - For MSIs, we have two windows in the address space (one at the top of
64 the 32-bit space and one much higher) which, via a combination of the
70 - Error messages just use the RTT.
81 - The M32 window:
87 32-bit PCIe accesses. We configure that window at boot from FW and
97 to be assigned to PEs on a segment granularity. For a 2GB window,
101 SR-IOV). We basically use the trick of forcing the bridge MMIO windows
103 can be assigned to a PE.
110 - The M64 windows:
[all …]
/kernel/linux/linux-6.6/Documentation/powerpc/
Dpci_iov_resource_on_powernv.rst57 - For DMA we then provide an entire address space for each PE that can
63 - For MSIs, we have two windows in the address space (one at the top of
64 the 32-bit space and one much higher) which, via a combination of the
70 - Error messages just use the RTT.
81 - The M32 window:
87 32-bit PCIe accesses. We configure that window at boot from FW and
97 to be assigned to PEs on a segment granularity. For a 2GB window,
101 SR-IOV). We basically use the trick of forcing the bridge MMIO windows
103 can be assigned to a PE.
110 - The M64 windows:
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/i2c/
Di2c-atr.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-atr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
22 i2c-alias-pool:
23 $ref: /schemas/types.yaml#/definitions/uint32-array
25 I2C alias pool is a pool of I2C addresses on the main I2C bus that can be
27 addresses must be available, not used by any other peripheral. Each
28 remote peripheral is assigned an alias from the pool, and transactions to

12345678910>>...31