| /kernel/linux/linux-6.6/arch/sparc/kernel/ |
| D | pci_sun4v.c | 80 return iommu->atu && mask > DMA_BIT_MASK(32); in iommu_use_atu()
119 iotsb_num = pbm->iommu->atu->iotsb->iotsb_num; in iommu_batch_flush()
127 pr_err_ratelimited("%s: ATU map of [%08lx:%lx:%llx:%lx:%lx] failed with status %ld\n", in iommu_batch_flush()
218 tbl = &iommu->atu->tbl; in dma_4v_alloc_coherent()
328 struct atu *atu; in dma_4v_free_coherent() local
337 atu = iommu->atu; in dma_4v_free_coherent()
344 tbl = &atu->tbl; in dma_4v_free_coherent()
345 iotsb_num = atu->iotsb->iotsb_num; in dma_4v_free_coherent()
361 struct atu *atu; in dma_4v_map_page() local
371 atu = iommu->atu; in dma_4v_map_page()
[all …]
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| /kernel/linux/linux-5.10/arch/sparc/kernel/ |
| D | pci_sun4v.c | 79 return iommu->atu && mask > DMA_BIT_MASK(32); in iommu_use_atu()
118 iotsb_num = pbm->iommu->atu->iotsb->iotsb_num; in iommu_batch_flush()
126 pr_err_ratelimited("%s: ATU map of [%08lx:%lx:%llx:%lx:%lx] failed with status %ld\n", in iommu_batch_flush()
217 tbl = &iommu->atu->tbl; in dma_4v_alloc_coherent()
327 struct atu *atu; in dma_4v_free_coherent() local
336 atu = iommu->atu; in dma_4v_free_coherent()
343 tbl = &atu->tbl; in dma_4v_free_coherent()
344 iotsb_num = atu->iotsb->iotsb_num; in dma_4v_free_coherent()
360 struct atu *atu; in dma_4v_map_page() local
370 atu = iommu->atu; in dma_4v_map_page()
[all …]
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| /kernel/linux/linux-6.6/drivers/net/dsa/mv88e6xxx/ |
| D | global1_atu.c | 3 * Marvell 88E6xxx Address Translation Unit (ATU) support
18 /* Offset 0x01: ATU FID Register */
25 /* Offset 0x0A: ATU Control Register */
110 /* Offset 0x0B: ATU Operation Register */
144 /* ATU DBNum[7:4] are located in ATU Control 15:12 */ in mv88e6xxx_g1_atu_op()
156 /* ATU DBNum[5:4] are located in ATU Operation 9:8 */ in mv88e6xxx_g1_atu_op()
160 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */ in mv88e6xxx_g1_atu_op()
192 /* ATU DBNum[7:4] are located in ATU Control 15:12 */ in mv88e6xxx_g1_atu_fid_read()
200 /* ATU DBNum[5:4] are located in ATU Operation 9:8 */ in mv88e6xxx_g1_atu_fid_read()
204 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */ in mv88e6xxx_g1_atu_fid_read()
[all …]
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| D | global1.h | 44 /* Offset 0x01: ATU FID Register */
112 /* Offset 0x0A: ATU Control Register */
117 /* Offset 0x0B: ATU Operation Register */
134 /* Offset 0x0C: ATU Data Register */
166 /* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1
167 * Offset 0x0E: ATU MAC Address Register Bytes 2 & 3
168 * Offset 0x0F: ATU MAC Address Register Bytes 4 & 5
|
| D | devlink.c | 112 dev_err(chip->dev, "failed to set ATU stats kind/bin\n"); in mv88e6xxx_devlink_atu_bin_get()
118 dev_err(chip->dev, "failed to perform ATU get next\n"); in mv88e6xxx_devlink_atu_bin_get()
124 dev_err(chip->dev, "failed to get ATU stats\n"); in mv88e6xxx_devlink_atu_bin_get()
187 err = dsa_devlink_resource_register(ds, "ATU", in mv88e6xxx_setup_devlink_resources()
304 /* The ATU entry varies between mv88e6xxx chipset generations. Define
676 .name = "atu",
|
| /kernel/linux/linux-5.10/drivers/net/dsa/mv88e6xxx/ |
| D | global1_atu.c | 3 * Marvell 88E6xxx Address Translation Unit (ATU) support
16 /* Offset 0x01: ATU FID Register */
23 /* Offset 0x0A: ATU Control Register */
108 /* Offset 0x0B: ATU Operation Register */
129 /* ATU DBNum[7:4] are located in ATU Control 15:12 */ in mv88e6xxx_g1_atu_op()
141 /* ATU DBNum[5:4] are located in ATU Operation 9:8 */ in mv88e6xxx_g1_atu_op()
145 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */ in mv88e6xxx_g1_atu_op()
162 /* Offset 0x0C: ATU Data Register */
198 /* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1
199 * Offset 0x0E: ATU MAC Address Register Bytes 2 & 3
[all …]
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| D | global1.h | 43 /* Offset 0x01: ATU FID Register */
109 /* Offset 0x0A: ATU Control Register */
114 /* Offset 0x0B: ATU Operation Register */
131 /* Offset 0x0C: ATU Data Register */
163 /* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1
164 * Offset 0x0E: ATU MAC Address Register Bytes 2 & 3
165 * Offset 0x0F: ATU MAC Address Register Bytes 4 & 5
|
| D | devlink.c | 112 dev_err(chip->dev, "failed to set ATU stats kind/bin\n"); in mv88e6xxx_devlink_atu_bin_get()
118 dev_err(chip->dev, "failed to perform ATU get next\n"); in mv88e6xxx_devlink_atu_bin_get()
124 dev_err(chip->dev, "failed to get ATU stats\n"); in mv88e6xxx_devlink_atu_bin_get()
187 err = dsa_devlink_resource_register(ds, "ATU", in mv88e6xxx_setup_devlink_resources()
304 /* The ATU entry varies between mv88e6xxx chipset generations. Define
473 .name = "atu",
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| /kernel/linux/linux-6.6/arch/sparc/include/asm/ |
| D | iommu_64.h | 30 /* Data structures for SPARC ATU architecture */
46 struct atu { struct
57 struct atu *atu; argument
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| /kernel/linux/linux-5.10/arch/sparc/include/asm/ |
| D | iommu_64.h | 30 /* Data structures for SPARC ATU architecture */
46 struct atu { struct
57 struct atu *atu; argument
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | designware-pcie.txt | 9 the configuration and ATU address space
10 - reg-names: Must be "config" for the PCIe configuration space and "atu" for
11 the ATU address space.
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| D | host-generic-pci.yaml | 68 DesignWare PCIe controller in RC mode with static ATU window mappings
72 is there any reason for the driver to reconfigure ATU windows for
75 In cases where the IP was synthesized with a minimum ATU window size
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| D | pci-keystone.txt | 81 TI specific application registers, "atu" for the
108 reg-names = "app", "dbics", "addr_space", "atu";
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| D | socionext,uniphier-pcie-ep.yaml | 41 - const: atu
|
| /kernel/linux/linux-5.10/drivers/pci/controller/dwc/ |
| D | pcie-designware.c | 194 dev_err(pci->dev, "Read ATU address failed\n"); in dw_pcie_readl_atu()
210 dev_err(pci->dev, "Write ATU address failed\n"); in dw_pcie_writel_atu()
254 * Make sure ATU enable takes effect before any subsequent config in dw_pcie_prog_outbound_atu_unroll()
300 * Make sure ATU enable takes effect before any subsequent config in __dw_pcie_prog_outbound_atu()
374 * Make sure ATU enable takes effect before any subsequent config in dw_pcie_prog_inbound_atu_unroll()
424 * Make sure ATU enable takes effect before any subsequent config in dw_pcie_prog_inbound_atu()
569 devm_platform_ioremap_resource_byname(pdev, "atu"); in dw_pcie_setup()
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/ |
| D | intel,keembay-pcie-ep.yaml | 24 - const: atu
62 reg-names = "dbi", "dbi2", "atu", "addr_space", "apb";
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| D | qcom,pcie-ep.yaml | 27 - description: Address Translation Unit (ATU) registers
36 - const: atu
193 reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
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| D | ti,am65-pci-ep.yaml | 29 - const: atu
70 reg-names = "app", "dbics", "addr_space", "atu";
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| D | intel,keembay-pcie.yaml | 32 - const: atu
83 reg-names = "dbi", "atu", "config", "apb";
|
| D | host-generic-pci.yaml | 68 DesignWare PCIe controller in RC mode with static ATU window mappings
72 is there any reason for the driver to reconfigure ATU windows for
75 In cases where the IP was synthesized with a minimum ATU window size
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| D | ti,am65-pci-host.yaml | 30 - const: atu
92 reg-names = "app", "dbics", "config", "atu";
|
| D | snps,dw-pcie-ep.yaml | 76 const: atu
104 - description: See native 'atu' CSR region for details.
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| D | snps,dw-pcie.yaml | 85 const: atu
110 - description: See native 'atu' CSR region for details.
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| /kernel/linux/linux-6.6/drivers/pci/controller/dwc/ |
| D | pcie-designware.c | 131 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu"); in dw_pcie_get_resources()
392 dev_err(pci->dev, "Read ATU address failed\n"); in dw_pcie_readl_atu()
412 dev_err(pci->dev, "Write ATU address failed\n"); in dw_pcie_writel_atu()
430 * bit in the Control register-1 of the ATU outbound region acts in dw_pcie_enable_ecrc()
438 * registers, the transactions going through ATU won't have TLP in dw_pcie_enable_ecrc()
512 * Make sure ATU enable takes effect before any subsequent config in __dw_pcie_prog_outbound_atu()
590 * Make sure ATU enable takes effect before any subsequent config in dw_pcie_prog_inbound_atu()
626 * Make sure ATU enable takes effect before any subsequent config in dw_pcie_prog_ep_inbound_atu()
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| /kernel/linux/linux-5.10/arch/arm/mach-iop32x/ |
| D | pci.c | 310 /* Flag to determine whether the ATU is initialized and the PCI bus scanned */
343 DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD); in iop3xx_atu_debug()
344 DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR); in iop3xx_atu_debug()
|