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/kernel/linux/linux-6.6/drivers/pinctrl/renesas/
Dsh_pfc.h1 /* SPDX-License-Identifier: GPL-2.0
12 #include <linux/pinctrl/pinconf-generic.h>
43 const char *name; member
50 .name = #alias, \
56 #define SH_PFC_PIN_GROUP(name) SH_PFC_PIN_GROUP_ALIAS(name, name) argument
62 .name = #_name, \
79 const char *name; member
86 .name = #n, \
92 const char *name; member
99 const char *name; member
[all …]
/kernel/linux/linux-6.6/tools/testing/selftests/gpio/
Dgpio-sim.sh2 # SPDX-License-Identifier: GPL-2.0
6 CONFIGFS_DIR="/sys/kernel/config/gpio-sim"
7 MODULE="gpio-sim"
25 BANK=`basename $FILE`
26 if [ "$BANK" = "live" -o "$BANK" = "dev_name" ]; then
30 LINES=`ls $CONFIGFS_DIR/$CHIP/$BANK/ | grep -E ^line`
33 if [ -e $CONFIGFS_DIR/$CHIP/$BANK/$LINE/hog ]; then
34 rmdir $CONFIGFS_DIR/$CHIP/$BANK/$LINE/hog || \
38 rmdir $CONFIGFS_DIR/$CHIP/$BANK/$LINE || \
43 rmdir $CONFIGFS_DIR/$CHIP/$BANK
[all …]
/kernel/linux/linux-5.10/drivers/pinctrl/renesas/
Dsh_pfc.h1 /* SPDX-License-Identifier: GPL-2.0
12 #include <linux/pinctrl/pinconf-generic.h>
39 const char *name; member
45 .name = #alias, \
54 const char *name; member
68 .name = #n#s#__VA_ARGS__, \
99 .name = #n, \
105 const char *name; member
112 const char *name; member
132 * - name: Register name (unused, for documentation purposes only)
[all …]
/kernel/linux/linux-6.6/drivers/pinctrl/samsung/
Dpinctrl-exynos.c1 // SPDX-License-Identifier: GPL-2.0+
27 #include <linux/soc/samsung/exynos-pmu.h>
28 #include <linux/soc/samsung/exynos-regs-pmu.h>
30 #include "pinctrl-samsung.h"
31 #include "pinctrl-exynos.h"
54 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_mask() local
55 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_mask()
59 raw_spin_lock_irqsave(&bank->slock, flags); in exynos_irq_mask()
61 mask = readl(bank->eint_base + reg_mask); in exynos_irq_mask()
62 mask |= 1 << irqd->hwirq; in exynos_irq_mask()
[all …]
Dpinctrl-samsung.c1 // SPDX-License-Identifier: GPL-2.0+
3 // pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
31 #include "pinctrl-samsung.h"
41 { "samsung,pin-pud", PINCFG_TYPE_PUD },
42 { "samsung,pin-drv", PINCFG_TYPE_DRV },
43 { "samsung,pin-con-pdn", PINCFG_TYPE_CON_PDN },
44 { "samsung,pin-pud-pdn", PINCFG_TYPE_PUD_PDN },
45 { "samsung,pin-val", PINCFG_TYPE_DAT },
54 return pmx->nr_groups; in samsung_get_group_count()
62 return pmx->pin_groups[group].name; in samsung_get_group_name()
[all …]
Dpinctrl-samsung.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25 * enum pincfg_type - possible pin configuration types supported.
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
65 * enum eint_type - possible external interrupt types.
66 * @EINT_TYPE_NONE: bank does not support external interrupts
67 * @EINT_TYPE_GPIO: bank supportes external gpio interrupts
68 * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
69 * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
[all …]
Dpinctrl-s3c64xx.c1 // SPDX-License-Identifier: GPL-2.0+
3 // S3C64xx specific support for pinctrl-samsung driver.
7 // Based on pinctrl-exynos.c, please see the file for original copyrights.
24 #include "pinctrl-samsung.h"
102 .name = id \
112 .eint_mask = (1 << (pins)) - 1, \
114 .name = id \
126 .name = id \
136 .eint_mask = (1 << (pins)) - 1, \
138 .name = id \
[all …]
/kernel/linux/linux-5.10/drivers/pinctrl/samsung/
Dpinctrl-exynos.c1 // SPDX-License-Identifier: GPL-2.0+
27 #include <linux/soc/samsung/exynos-pmu.h>
28 #include <linux/soc/samsung/exynos-regs-pmu.h>
30 #include <dt-bindings/pinctrl/samsung.h>
32 #include "pinctrl-samsung.h"
33 #include "pinctrl-exynos.h"
56 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_mask() local
57 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_mask()
61 spin_lock_irqsave(&bank->slock, flags); in exynos_irq_mask()
63 mask = readl(bank->eint_base + reg_mask); in exynos_irq_mask()
[all …]
Dpinctrl-samsung.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25 * enum pincfg_type - possible pin configuration types supported.
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
57 * enum eint_type - possible external interrupt types.
58 * @EINT_TYPE_NONE: bank does not support external interrupts
59 * @EINT_TYPE_GPIO: bank supportes external gpio interrupts
60 * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
61 * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
[all …]
Dpinctrl-samsung.c1 // SPDX-License-Identifier: GPL-2.0+
3 // pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
28 #include <dt-bindings/pinctrl/samsung.h>
31 #include "pinctrl-samsung.h"
41 { "samsung,pin-pud", PINCFG_TYPE_PUD },
42 { "samsung,pin-drv", PINCFG_TYPE_DRV },
43 { "samsung,pin-con-pdn", PINCFG_TYPE_CON_PDN },
44 { "samsung,pin-pud-pdn", PINCFG_TYPE_PUD_PDN },
45 { "samsung,pin-val", PINCFG_TYPE_DAT },
54 return pmx->nr_groups; in samsung_get_group_count()
[all …]
Dpinctrl-s3c64xx.c1 // SPDX-License-Identifier: GPL-2.0+
3 // S3C64xx specific support for pinctrl-samsung driver.
7 // Based on pinctrl-exynos.c, please see the file for original copyrights.
24 #include "pinctrl-samsung.h"
102 .name = id \
112 .eint_mask = (1 << (pins)) - 1, \
114 .name = id \
126 .name = id \
136 .eint_mask = (1 << (pins)) - 1, \
138 .name = id \
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/kernel/linux/linux-6.6/drivers/crypto/intel/qat/qat_common/
Dadf_transport_debug.c1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
2 /* Copyright(c) 2014 - 2020 Intel Corporation */
15 struct adf_etr_ring_data *ring = sfile->private; in adf_ring_start()
21 if (*pos >= (ADF_SIZE_TO_RING_SIZE_IN_BYTES(ring->ring_size) / in adf_ring_start()
22 ADF_MSG_SIZE_TO_BYTES(ring->msg_size))) in adf_ring_start()
25 return ring->base_addr + in adf_ring_start()
26 (ADF_MSG_SIZE_TO_BYTES(ring->msg_size) * (*pos)++); in adf_ring_start()
31 struct adf_etr_ring_data *ring = sfile->private; in adf_ring_next()
33 if (*pos >= (ADF_SIZE_TO_RING_SIZE_IN_BYTES(ring->ring_size) / in adf_ring_next()
34 ADF_MSG_SIZE_TO_BYTES(ring->msg_size))) in adf_ring_next()
[all …]
/kernel/linux/linux-5.10/drivers/crypto/qat/qat_common/
Dadf_transport_debug.c1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
2 /* Copyright(c) 2014 - 2020 Intel Corporation */
15 struct adf_etr_ring_data *ring = sfile->private; in adf_ring_start()
21 if (*pos >= (ADF_SIZE_TO_RING_SIZE_IN_BYTES(ring->ring_size) / in adf_ring_start()
22 ADF_MSG_SIZE_TO_BYTES(ring->msg_size))) in adf_ring_start()
25 return ring->base_addr + in adf_ring_start()
26 (ADF_MSG_SIZE_TO_BYTES(ring->msg_size) * (*pos)++); in adf_ring_start()
31 struct adf_etr_ring_data *ring = sfile->private; in adf_ring_next()
33 if (*pos >= (ADF_SIZE_TO_RING_SIZE_IN_BYTES(ring->ring_size) / in adf_ring_next()
34 ADF_MSG_SIZE_TO_BYTES(ring->msg_size))) in adf_ring_next()
[all …]
/kernel/linux/linux-6.6/arch/x86/kernel/cpu/mce/
Damd.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * (c) 2005-2016 Advanced Micro Devices, Inc.
5 * Written by Jacob Shin - AMD, Inc.
84 u8 sysfs_id; /* Value used for sysfs name. */
91 const char *name; /* Short name for sysfs */ member
92 const char *long_name; /* Long name for pretty-printing */
133 return smca_names[t].name; in smca_get_name()
145 enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank) in smca_get_bank_type() argument
149 if (bank >= MAX_NR_BANKS) in smca_get_bank_type()
152 b = &per_cpu(smca_banks, cpu)[bank]; in smca_get_bank_type()
[all …]
/kernel/linux/linux-5.10/drivers/pinctrl/
Dpinctrl-equilibrium.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/pinctrl/pinconf-generic.h>
18 #include "pinctrl-equilibrium.h"
20 #define PIN_NAME_FMT "io-%d"
31 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_gpio_disable_irq()
32 writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR); in eqbr_gpio_disable_irq()
33 raw_spin_unlock_irqrestore(&gctrl->lock, flags); in eqbr_gpio_disable_irq()
43 gc->direction_input(gc, offset); in eqbr_gpio_enable_irq()
44 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_gpio_enable_irq()
45 writel(BIT(offset), gctrl->membase + GPIO_IRNRNSET); in eqbr_gpio_enable_irq()
[all …]
Dpinctrl-st.c1 // SPDX-License-Identifier: GPL-2.0-only
60 * There are two registers cfg0 and cfg1 in this style for each bank.
61 * Each field in this register is 8 bit corresponding to 8 pins in the bank.
96 * (direction, retime-type, retime-clk, retime-delay)
98 * +----------------+
99 *[31:28]| reserved-3 |
100 * +----------------+-------------
102 * +----------------+ v
104 * +----------------+ ^
106 * +----------------+-------------
[all …]
Dpinctrl-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * With some ideas taken from pinctrl-samsung:
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
29 #include <linux/pinctrl/pinconf-generic.h>
34 #include <dt-bindings/pinctrl/rockchip.h>
88 * @offset: if initialized to -1 it will be autocalculated, by specifying
121 * @offset: if initialized to -1 it will be autocalculated, by specifying
134 * @reg_base: register base of the gpio bank
136 * @clk: clock of the gpio bank
[all …]
/kernel/linux/linux-6.6/drivers/pinctrl/
Dpinctrl-equilibrium.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/pinctrl/pinconf-generic.h>
19 #include "pinctrl-equilibrium.h"
21 #define PIN_NAME_FMT "io-%d"
32 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_gpio_disable_irq()
33 writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR); in eqbr_gpio_disable_irq()
34 raw_spin_unlock_irqrestore(&gctrl->lock, flags); in eqbr_gpio_disable_irq()
45 gc->direction_input(gc, offset); in eqbr_gpio_enable_irq()
47 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_gpio_enable_irq()
48 writel(BIT(offset), gctrl->membase + GPIO_IRNRNSET); in eqbr_gpio_enable_irq()
[all …]
Dpinctrl-st.c1 // SPDX-License-Identifier: GPL-2.0-only
64 * There are two registers cfg0 and cfg1 in this style for each bank.
65 * Each field in this register is 8 bit corresponding to 8 pins in the bank.
100 * (direction, retime-type, retime-clk, retime-delay)
102 * +----------------+
103 *[31:28]| reserved-3 |
104 * +----------------+-------------
106 * +----------------+ v
108 * +----------------+ ^
110 * +----------------+-------------
[all …]
/kernel/linux/linux-5.10/drivers/pinctrl/sunxi/
Dpinctrl-sunxi.h6 * Maxime Ripard <maxime.ripard@free-electrons.com>
32 #define SUNXI_PINCTRL_PIN(bank, pin) \ argument
33 PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
62 #define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1)
66 #define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1)
70 #define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1)
118 const char *name; member
142 const char *name; member
148 const char *name; member
192 .name = _name, \
[all …]
/kernel/linux/linux-5.10/arch/x86/kernel/cpu/mce/
Damd.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * (c) 2005-2016 Advanced Micro Devices, Inc.
5 * Written by Jacob Shin - AMD, Inc.
75 const char *name; /* Short name for sysfs */ member
76 const char *long_name; /* Long name for pretty-printing */
108 return smca_names[t].name; in smca_get_name()
120 static enum smca_bank_types smca_get_bank_type(unsigned int bank) in smca_get_bank_type() argument
124 if (bank >= MAX_NR_BANKS) in smca_get_bank_type()
127 b = &smca_banks[bank]; in smca_get_bank_type()
128 if (!b->hwid) in smca_get_bank_type()
[all …]
/kernel/linux/linux-6.6/drivers/gpio/
Dgpio-sim.c1 // SPDX-License-Identifier: GPL-2.0-or-later
70 gc = &chip->gc; in gpio_sim_apply_pull()
71 desc = &gc->gpiodev->descs[offset]; in gpio_sim_apply_pull()
73 guard(mutex)(&chip->lock); in gpio_sim_apply_pull()
75 if (test_bit(FLAG_REQUESTED, &desc->flags) && in gpio_sim_apply_pull()
76 !test_bit(FLAG_IS_OUT, &desc->flags)) { in gpio_sim_apply_pull()
77 if (value == !!test_bit(offset, chip->value_map)) in gpio_sim_apply_pull()
81 * This is fine - it just means, nobody is listening in gpio_sim_apply_pull()
86 irq = irq_find_mapping(chip->irq_sim, offset); in gpio_sim_apply_pull()
103 if (!test_bit(FLAG_REQUESTED, &desc->flags) || in gpio_sim_apply_pull()
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-omap2/
Dpowerdomain.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
6 * Copyright (C) 2007-2011 Nokia Corporation
65 static struct powerdomain *_pwrdm_lookup(const char *name) in _pwrdm_lookup() argument
72 if (!strcmp(name, temp_pwrdm->name)) { in _pwrdm_lookup()
82 * _pwrdm_register - register a powerdomain
86 * -EINVAL if given a null pointer, -EEXIST if a powerdomain is
87 * already registered by the provided name, or 0 upon success.
94 if (!pwrdm || !pwrdm->name) in _pwrdm_register()
95 return -EINVAL; in _pwrdm_register()
[all …]
/kernel/linux/linux-6.6/drivers/pinctrl/sunxi/
Dpinctrl-sunxi.h6 * Maxime Ripard <maxime.ripard@free-electrons.com>
32 #define SUNXI_PINCTRL_PIN(bank, pin) \ argument
33 PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
58 #define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1)
62 #define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1)
66 #define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1)
123 const char *name; member
147 const char *name; member
153 const char *name; member
200 .name = _name, \
[all …]
/kernel/linux/linux-5.10/drivers/uio/
Duio_fsl_elbc_gpcm.c1 // SPDX-License-Identifier: GPL-2.0
9 using the general purpose chip-select mode (GPCM).
17 compatible = "fsl,elbc-gpcm-uio";
19 elbc-gpcm-br = <0xff810800>;
20 elbc-gpcm-or = <0xffff09f7>;
21 interrupt-parent = <&mpic>;
25 netx5152,init-win0-offset = <0x0>;
29 Only the entries reg (to identify bank) and elbc-gpcm-* (initial BR/OR
31 are optional (as well as any type-specific options such as
32 netx5152,init-win0-offset). As long as no interrupt handler is needed,
[all …]

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