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/kernel/linux/linux-5.10/drivers/clk/ux500/
Du8500_of_clk.c65 u32 bases[CLKRST_MAX]; in u8500_clk_init() local
68 for (i = 0; i < ARRAY_SIZE(bases); i++) { in u8500_clk_init()
75 bases[i] = r.start; in u8500_clk_init()
255 clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
259 clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
263 clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
267 clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
271 clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
275 clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
279 clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
[all …]
/kernel/linux/linux-6.6/drivers/clk/ux500/
Du8500_of_clk.c131 u32 bases[CLKRST_MAX]; in u8500_clk_init() local
144 for (i = 0; i < ARRAY_SIZE(bases); i++) { in u8500_clk_init()
151 bases[i] = r.start; in u8500_clk_init()
303 clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
307 clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
311 clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
315 clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
319 clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
323 clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
327 clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
[all …]
Dreset-prcc.h13 * @base: the remapped PRCC bases
/kernel/linux/linux-5.10/arch/arm/mach-davinci/
Dasp.h8 /* Bases of dm644x and dm355 register banks */
12 /* Bases of dm365 register banks */
15 /* Bases of dm646x register banks */
19 /* Bases of da850/da830 McASP0 register banks */
22 /* Bases of da830 McASP1 register banks */
25 /* Bases of da830 McASP2 register banks */
/kernel/linux/linux-5.10/drivers/iommu/
Drockchip-iommu.c101 void __iomem **bases; member
290 writel(command, iommu->bases[i] + RK_MMU_COMMAND); in rk_iommu_command()
310 rk_iommu_write(iommu->bases[i], RK_MMU_ZAP_ONE_LINE, iova); in rk_iommu_zap_lines()
320 active &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) & in rk_iommu_is_stall_active()
332 enable &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) & in rk_iommu_is_paging_enabled()
344 done &= rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR) == 0; in rk_iommu_is_reset_done()
369 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); in rk_iommu_enable_stall()
390 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); in rk_iommu_disable_stall()
411 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); in rk_iommu_enable_paging()
432 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); in rk_iommu_disable_paging()
[all …]
/kernel/linux/linux-5.10/include/linux/
Dposix-timers.h118 * @bases: Base container for posix CPU clocks
127 struct posix_cputimer_base bases[CPUCLOCK_MAX]; member
147 pct->bases[0].nextevt = U64_MAX; in posix_cputimers_init()
148 pct->bases[1].nextevt = U64_MAX; in posix_cputimers_init()
149 pct->bases[2].nextevt = U64_MAX; in posix_cputimers_init()
157 pct->bases[CPUCLOCK_SCHED].nextevt = runtime; in posix_cputimers_rt_watchdog()
173 .bases = INIT_CPU_TIMERBASES(s.posix_cputimers.bases), \
Dhrtimer.h186 * struct hrtimer_cpu_base - the per cpu clock bases
187 * @lock: lock protecting the base and associated clock bases
190 * @active_bases: Bitfield to mark bases with active timers
212 * @clock_base: array of clock bases for this cpu
/kernel/linux/linux-6.6/include/linux/
Dposix-timers.h124 * @bases: Base container for posix CPU clocks
133 struct posix_cputimer_base bases[CPUCLOCK_MAX]; member
153 pct->bases[0].nextevt = U64_MAX; in posix_cputimers_init()
154 pct->bases[1].nextevt = U64_MAX; in posix_cputimers_init()
155 pct->bases[2].nextevt = U64_MAX; in posix_cputimers_init()
163 pct->bases[CPUCLOCK_SCHED].nextevt = runtime; in posix_cputimers_rt_watchdog()
179 .bases = INIT_CPU_TIMERBASES(s.posix_cputimers.bases), \
Dhrtimer.h183 * struct hrtimer_cpu_base - the per cpu clock bases
184 * @lock: lock protecting the base and associated clock bases
187 * @active_bases: Bitfield to mark bases with active timers
209 * @clock_base: array of clock bases for this cpu
/kernel/linux/linux-6.6/drivers/iommu/
Drockchip-iommu.c107 void __iomem **bases; member
350 writel(command, iommu->bases[i] + RK_MMU_COMMAND); in rk_iommu_command()
370 rk_iommu_write(iommu->bases[i], RK_MMU_ZAP_ONE_LINE, iova); in rk_iommu_zap_lines()
380 active &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) & in rk_iommu_is_stall_active()
392 enable &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) & in rk_iommu_is_paging_enabled()
404 done &= rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR) == 0; in rk_iommu_is_reset_done()
429 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); in rk_iommu_enable_stall()
450 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); in rk_iommu_disable_stall()
471 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); in rk_iommu_enable_paging()
492 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); in rk_iommu_disable_paging()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/host1x/
Dsyncpt.c26 struct host1x_syncpt_base *bases = host->bases; in host1x_syncpt_base_request() local
30 if (!bases[i].requested) in host1x_syncpt_base_request()
36 bases[i].requested = true; in host1x_syncpt_base_request()
37 return &bases[i]; in host1x_syncpt_base_request()
282 struct host1x_syncpt_base *bases; in host1x_syncpt_init() local
291 bases = devm_kcalloc(host->dev, host->info->nb_bases, sizeof(*bases), in host1x_syncpt_init()
293 if (!bases) in host1x_syncpt_init()
302 bases[i].id = i; in host1x_syncpt_init()
306 host->bases = bases; in host1x_syncpt_init()
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/dispnv50/
Dbase.c33 } bases[] = { in nv50_base_new() local
46 cid = nvif_mclass(&disp->disp->object, bases); in nv50_base_new()
52 return bases[cid].new(drm, head, bases[cid].oclass, pwndw); in nv50_base_new()
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/dispnv50/
Dbase.c33 } bases[] = { in nv50_base_new() local
46 cid = nvif_mclass(&disp->disp->object, bases); in nv50_base_new()
52 return bases[cid].new(drm, head, bases[cid].oclass, pwndw); in nv50_base_new()
/kernel/linux/linux-5.10/drivers/gpu/host1x/
Dsyncpt.c25 struct host1x_syncpt_base *bases = host->bases; in host1x_syncpt_base_request() local
29 if (!bases[i].requested) in host1x_syncpt_base_request()
35 bases[i].requested = true; in host1x_syncpt_base_request()
36 return &bases[i]; in host1x_syncpt_base_request()
367 struct host1x_syncpt_base *bases; in host1x_syncpt_init() local
376 bases = devm_kcalloc(host->dev, host->info->nb_bases, sizeof(*bases), in host1x_syncpt_init()
378 if (!bases) in host1x_syncpt_init()
394 bases[i].id = i; in host1x_syncpt_init()
398 host->bases = bases; in host1x_syncpt_init()
/kernel/linux/linux-6.6/include/xen/interface/
Dmemory.h27 * OUT: MFN (*not* GMFN) bases of extents that were allocated
29 * IN: GMFN bases of extents to free
31 * IN: GPFN bases of extents to populate with memory
32 * OUT: GMFN bases of extents that were allocated
68 * [IN] Details of memory extents to be exchanged (GMFN bases).
80 * 4. @out.extent_start lists GPFN bases to be populated
81 * 5. @out.extent_start is overwritten with allocated GMFN bases
116 * Returns a list of MFN bases of 2MB extents comprising the machine_to_phys
/kernel/linux/linux-5.10/include/xen/interface/
Dmemory.h27 * OUT: MFN (*not* GMFN) bases of extents that were allocated
29 * IN: GMFN bases of extents to free
31 * IN: GPFN bases of extents to populate with memory
32 * OUT: GMFN bases of extents that were allocated
68 * [IN] Details of memory extents to be exchanged (GMFN bases).
80 * 4. @out.extent_start lists GPFN bases to be populated
81 * 5. @out.extent_start is overwritten with allocated GMFN bases
116 * Returns a list of MFN bases of 2MB extents comprising the machine_to_phys
/kernel/linux/linux-5.10/drivers/iommu/arm/arm-smmu/
Darm-smmu-nvidia.c27 void __iomem *bases[NUM_SMMU_INSTANCES]; member
36 return nvidia_smmu->bases[inst] + (page << smmu->pgshift); in nvidia_smmu_page()
258 nvidia_smmu->bases[0] = smmu->base; in nvidia_smmu_impl_init()
264 nvidia_smmu->bases[1] = devm_ioremap_resource(dev, res); in nvidia_smmu_impl_init()
265 if (IS_ERR(nvidia_smmu->bases[1])) in nvidia_smmu_impl_init()
266 return ERR_CAST(nvidia_smmu->bases[1]); in nvidia_smmu_impl_init()
/kernel/linux/linux-6.6/drivers/iommu/arm/arm-smmu/
Darm-smmu-nvidia.c36 void __iomem *bases[MAX_SMMU_INSTANCES]; member
52 return nvidia_smmu->bases[inst] + (page << smmu->pgshift); in nvidia_smmu_page()
324 nvidia_smmu->bases[0] = smmu->base; in nvidia_smmu_impl_init()
332 nvidia_smmu->bases[i] = devm_ioremap_resource(dev, res); in nvidia_smmu_impl_init()
333 if (IS_ERR(nvidia_smmu->bases[i])) in nvidia_smmu_impl_init()
334 return ERR_CAST(nvidia_smmu->bases[i]); in nvidia_smmu_impl_init()
/kernel/linux/linux-5.10/kernel/time/
Dposix-cpu-timers.c27 pct->bases[CPUCLOCK_PROF].nextevt = cpu_limit * NSEC_PER_SEC; in posix_cputimers_group_init()
34 * tsk->signal->posix_cputimers.bases[clock].nextevt expiration cache if
147 return !(~pct->bases[CPUCLOCK_PROF].nextevt | in expiry_cache_is_inactive()
148 ~pct->bases[CPUCLOCK_VIRT].nextevt | in expiry_cache_is_inactive()
149 ~pct->bases[CPUCLOCK_SCHED].nextevt); in expiry_cache_is_inactive()
476 cleanup_timerqueue(&pct->bases[CPUCLOCK_PROF].tqhead); in cleanup_timers()
477 cleanup_timerqueue(&pct->bases[CPUCLOCK_VIRT].tqhead); in cleanup_timers()
478 cleanup_timerqueue(&pct->bases[CPUCLOCK_SCHED].tqhead); in cleanup_timers()
507 base = p->posix_cputimers.bases + clkidx; in arm_timer()
509 base = p->signal->posix_cputimers.bases + clkidx; in arm_timer()
[all …]
/kernel/linux/linux-6.6/kernel/time/
Dposix-cpu-timers.c28 pct->bases[CPUCLOCK_PROF].nextevt = cpu_limit * NSEC_PER_SEC; in posix_cputimers_group_init()
35 * tsk->signal->posix_cputimers.bases[clock].nextevt expiration cache if
154 return !(~pct->bases[CPUCLOCK_PROF].nextevt | in expiry_cache_is_inactive()
155 ~pct->bases[CPUCLOCK_VIRT].nextevt | in expiry_cache_is_inactive()
156 ~pct->bases[CPUCLOCK_SCHED].nextevt); in expiry_cache_is_inactive()
422 return tsk->posix_cputimers.bases + clkidx; in timer_base()
424 return tsk->signal->posix_cputimers.bases + clkidx; in timer_base()
533 cleanup_timerqueue(&pct->bases[CPUCLOCK_PROF].tqhead); in cleanup_timers()
534 cleanup_timerqueue(&pct->bases[CPUCLOCK_VIRT].tqhead); in cleanup_timers()
535 cleanup_timerqueue(&pct->bases[CPUCLOCK_SCHED].tqhead); in cleanup_timers()
[all …]
Dhrtimer.c64 * The timer bases:
66 * There are more clockids than hrtimer bases. Thus, we index
67 * into the timer bases by the hrtimer_base_type enum. When trying
570 * the clock bases so the result might be negative. Fix it up in __hrtimer_next_event_base()
585 * When a softirq is pending, we can ignore the HRTIMER_ACTIVE_SOFT bases,
587 * hrtimer_run_softirq(), hrtimer_update_softirq_timer() will re-add these bases.
589 * Therefore softirq values are those from the HRTIMER_ACTIVE_SOFT clock bases.
630 * soft bases. They will be handled in the already raised soft in hrtimer_update_next_event()
887 * clock bases and reprogram the clock event device. in hrtimer_reprogram()
910 * bases. Either it will see the update before handling a base or in update_needs_ipi()
[all …]
/kernel/linux/linux-5.10/arch/x86/boot/
Dearly_serial_console.c77 static const int bases[] = { 0x3f8, 0x2f8 }; in parse_earlyprintk() local
86 port = bases[idx]; in parse_earlyprintk()
/kernel/linux/linux-6.6/arch/x86/boot/
Dearly_serial_console.c77 static const int bases[] = { 0x3f8, 0x2f8 }; in parse_earlyprintk() local
86 port = bases[idx]; in parse_earlyprintk()
/kernel/linux/linux-5.10/drivers/ide/
Dbuddha.c43 * Bases of the IDE interfaces (relative to the board address)
62 * Offsets from one of the above bases
/kernel/linux/linux-6.6/arch/mips/include/asm/mach-loongson32/
Dloongson1.h17 /* Loongson 1 Register Bases */

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