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/kernel/linux/linux-5.10/drivers/pinctrl/zte/
Dpinctrl-zx.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 * struct zx_mux_desc - hardware mux descriptor
12 * @name: mux function name
13 * @muxval: mux register bit value
21 * struct zx_pin_data - hardware per-pin data
24 * @bitpos: bit position within TOP pinmux register
25 * @width: bit width within TOP pinmux register
27 * @cbitpos: pinconf bit position within AON register
28 * @muxes: available mux function names and corresponding register values
31 * arbitrarily, AON pinmux register bits are well organized per pin id, and
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/
Dpinctrl-single.txt1 One-register-per-pin type device tree based pinctrl driver
4 - compatible : "pinctrl-single" or "pinconf-single".
5 "pinctrl-single" means that pinconf isn't supported.
6 "pinconf-single" means that generic pinconf is supported.
8 - reg : offset and length of the register set for the mux registers
10 - #pinctrl-cells : number of cells in addition to the index, set to 1
11 for pinctrl-single,pins and 2 for pinctrl-single,bits
13 - pinctrl-single,register-width : pinmux register access width in bits
15 - pinctrl-single,function-mask : mask of allowed pinmux function bits
19 - pinctrl-single,function-off : function off mode for disabled state if
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Dbrcm,bcm2835-gpio.txt7 - compatible: "brcm,bcm2835-gpio"
8 - compatible: should be one of:
9 "brcm,bcm2835-gpio" - BCM2835 compatible pinctrl
10 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
11 "brcm,bcm2711-gpio" - BCM2711 compatible pinctrl
12 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
13 - reg: Should contain the physical address of the GPIO module's registers.
14 - gpio-controller: Marks the device node as a GPIO controller.
15 - #gpio-cells : Should be two. The first cell is the pin number and the
17 - bit 0 specifies polarity (0 for normal, 1 for inverted)
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/kernel/linux/linux-6.6/arch/arm/boot/dts/ti/omap/
Ddra7xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 atl_clkin0_ck: clock-atl-clkin0 {
9 #clock-cells = <0>;
10 compatible = "ti,dra7-atl-clock";
11 clock-output-names = "atl_clkin0_ck";
15 atl_clkin1_ck: clock-atl-clkin1 {
16 #clock-cells = <0>;
17 compatible = "ti,dra7-atl-clock";
18 clock-output-names = "atl_clkin1_ck";
22 atl_clkin2_ck: clock-atl-clkin2 {
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Dam43xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 sys_clkin_ck: clock-sys-clkin-31@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
13 ti,bit-shift = <31>;
17 crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 {
18 #clock-cells = <0>;
19 compatible = "ti,mux-clock";
20 clock-output-names = "crystal_freq_sel_ck";
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Dam33xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 sys_clkin_ck: clock-sys-clkin-22@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
13 ti,bit-shift = <22>;
17 adc_tsc_fck: clock-adc-tsc-fck {
18 #clock-cells = <0>;
19 compatible = "fixed-factor-clock";
20 clock-output-names = "adc_tsc_fck";
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/
Dbrcm,bcm2835-gpio.txt7 - compatible: "brcm,bcm2835-gpio"
8 - compatible: should be one of:
9 "brcm,bcm2835-gpio" - BCM2835 compatible pinctrl
10 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
11 "brcm,bcm2711-gpio" - BCM2711 compatible pinctrl
12 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
13 - reg: Should contain the physical address of the GPIO module's registers.
14 - gpio-controller: Marks the device node as a GPIO controller.
15 - #gpio-cells : Should be two. The first cell is the pin number and the
17 - bit 0 specifies polarity (0 for normal, 1 for inverted)
[all …]
Dpinctrl-single.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
21 - enum:
22 - pinctrl-single
23 - pinconf-single
24 - items:
25 - enum:
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dimx7s.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 #include <dt-bindings/clock/imx7d-clock.h>
7 #include <dt-bindings/power/imx7-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/imx7-reset.h>
12 #include "imx7d-pinfunc.h"
15 #address-cells = <1>;
16 #size-cells = <1>;
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Dbrcm,bcm7120-l2-intc.txt1 Broadcom BCM7120-style Level 2 interrupt controller
4 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
9 - outputs multiple interrupts signals towards its interrupt controller parent
11 - controls how some of the interrupts will be flowing, whether they will
16 - has one 32-bit enable word and one 32-bit status word
18 - no atomic set/clear operations
20 - not all bits within the interrupt controller actually map to an interrupt
26 0 -----[ MUX ] ------------|==========> GIC interrupt 75
27 \-----------\
29 1 -----[ MUX ] --------)---|==========> GIC interrupt 76
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/kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/imx/
Dimx7s.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 #include <dt-bindings/clock/imx7d-clock.h>
7 #include <dt-bindings/power/imx7-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/imx7-reset.h>
12 #include "imx7d-pinfunc.h"
15 #address-cells = <1>;
16 #size-cells = <1>;
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/kernel/linux/linux-6.6/sound/pci/ca0106/
Dca0106.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) 2004 James Courtier-Dutton <James@superbug.demon.co.uk>
4 * Driver CA0106 chips. e.g. Sound Blaster Audigy LS and Live 24bit
11 * Support interrupts per period.
48 * Added GPIO info for SB Live 24bit.
50 * Implement support for Line-in capture on SB Live 24bit.
52 * Add support for mute control on SB Live 24bit (cards w/ SPI DAC)
73 #define IPR_MIDI_RX_B 0x00020000 /* MIDI UART-B Receive buffer non-empty */
74 #define IPR_MIDI_TX_B 0x00010000 /* MIDI UART-B Transmit buffer empty */
87 #define IPR_MIDI_RX_A 0x00000004 /* MIDI UART-A Receive buffer non-empty */
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/kernel/linux/linux-5.10/sound/pci/ca0106/
Dca0106.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) 2004 James Courtier-Dutton <James@superbug.demon.co.uk>
4 * Driver CA0106 chips. e.g. Sound Blaster Audigy LS and Live 24bit
11 * Support interrupts per period.
48 * Added GPIO info for SB Live 24bit.
50 * Implement support for Line-in capture on SB Live 24bit.
52 * Add support for mute control on SB Live 24bit (cards w/ SPI DAC)
73 #define IPR_MIDI_RX_B 0x00020000 /* MIDI UART-B Receive buffer non-empty */
74 #define IPR_MIDI_TX_B 0x00010000 /* MIDI UART-B Transmit buffer empty */
87 #define IPR_MIDI_RX_A 0x00000004 /* MIDI UART-A Receive buffer non-empty */
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/kernel/linux/linux-6.6/include/net/
Dkcm.h1 /* SPDX-License-Identifier: GPL-2.0-only */
60 struct kcm_mux *mux; member
76 /* Don't use bit fields here, these are set under different locks */
93 struct kcm_mux *mux; member
123 /* Per net MUX list */
133 /* Structure for a MUX */
139 struct list_head kcm_socks; /* All KCM sockets on MUX */
140 int kcm_socks_cnt; /* Total KCM socket count for MUX */
141 struct list_head psocks; /* List of all psocks on MUX */
155 spinlock_t lock ____cacheline_aligned_in_smp; /* TX and mux locking */
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/kernel/linux/linux-5.10/include/net/
Dkcm.h1 /* SPDX-License-Identifier: GPL-2.0-only */
60 struct kcm_mux *mux; member
75 /* Don't use bit fields here, these are set under different locks */
92 struct kcm_mux *mux; member
122 /* Per net MUX list */
132 /* Structure for a MUX */
138 struct list_head kcm_socks; /* All KCM sockets on MUX */
139 int kcm_socks_cnt; /* Total KCM socket count for MUX */
140 struct list_head psocks; /* List of all psocks on MUX */
154 spinlock_t lock ____cacheline_aligned_in_smp; /* TX and mux locking */
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/
Dbrcm,bcm7120-l2-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM7120-style Level 2 and Broadcom BCM3380 Level 1 / Level 2
10 - Florian Fainelli <f.fainelli@gmail.com>
14 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
19 - outputs multiple interrupts signals towards its interrupt controller parent
21 - controls how some of the interrupts will be flowing, whether they will
26 - has one 32-bit enable word and one 32-bit status word
[all …]
/kernel/linux/linux-6.6/arch/hexagon/include/asm/
Dbitops.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Bit operations for the Hexagon architecture
5 * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
20 * (i.e. I get to shift by #5-2 (32 bits per long, 4 bytes per access),
23 * Typically, R10 is clobbered for address, R11 bit nr, and R12 is temp
27 * test_and_clear_bit - clear a bit and return its old value
28 * @nr: bit number to clear
41 " {if (!P1) jump 1b; %0 = mux(P0,#1,#0);}\n" in test_and_clear_bit()
51 * test_and_set_bit - set a bit and return its old value
52 * @nr: bit number to set
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/kernel/linux/linux-5.10/arch/hexagon/include/asm/
Dbitops.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Bit operations for the Hexagon architecture
5 * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
20 * (i.e. I get to shift by #5-2 (32 bits per long, 4 bytes per access),
23 * Typically, R10 is clobbered for address, R11 bit nr, and R12 is temp
27 * test_and_clear_bit - clear a bit and return its old value
28 * @nr: bit number to clear
41 " {if (!P1) jump 1b; %0 = mux(P0,#1,#0);}\n" in test_and_clear_bit()
51 * test_and_set_bit - set a bit and return its old value
52 * @nr: bit number to set
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/kernel/linux/linux-6.6/include/linux/mfd/
Dintel-m10-bmc.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2018-2020 Intel Corporation, Inc.
55 #define DRBL_RSU_REQUEST BIT(0)
59 #define DRBL_PKVL_EEPROM_LOAD_SEC BIT(24)
60 #define DRBL_PKVL1_POLL_EN BIT(25)
61 #define DRBL_PKVL2_POLL_EN BIT(26)
62 #define DRBL_CONFIG_SEL BIT(28)
63 #define DRBL_REBOOT_REQ BIT(29)
64 #define DRBL_REBOOT_DISABLED BIT(30)
126 /* Address of 4KB inverted bit vector containing staging area FLASH count */
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Domap-gpmc.txt7 - compatible: Should be set to one of the following:
9 ti,omap2420-gpmc (omap2420)
10 ti,omap2430-gpmc (omap2430)
11 ti,omap3430-gpmc (omap3430 & omap3630)
12 ti,omap4430-gpmc (omap4430 & omap4460 & omap543x)
13 ti,am3352-gpmc (am335x devices)
15 - reg: A resource specifier for the register space
17 - ti,hwmods: Should be set to "ti,gpmc" until the DT transition is
19 - #address-cells: Must be set to 2 to allow memory address translation
20 - #size-cells: Must be set to 1 to allow CS address passing
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/kernel/linux/linux-5.10/drivers/pinctrl/
Dpinctrl-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * With some ideas taken from pinctrl-samsung:
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
29 #include <linux/pinctrl/pinconf-generic.h>
34 #include <dt-bindings/pinctrl/rockchip.h>
69 * Generate a bitmask for setting a value (v) with a write mask bit in hiword
78 #define IOMUX_GPIO_ONLY BIT(0)
79 #define IOMUX_WIDTH_4BIT BIT(1)
80 #define IOMUX_SOURCE_PMU BIT(2)
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/kernel/linux/linux-5.10/arch/c6x/platforms/
Dmegamod-pic.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <asm/megamod-pic.h>
52 /* hw mux mapping */
69 u32 __iomem *evtmask = &pic->regs->evtmask[src / 32]; in mask_megamod()
71 raw_spin_lock(&pic->lock); in mask_megamod()
73 raw_spin_unlock(&pic->lock); in mask_megamod()
80 u32 __iomem *evtmask = &pic->regs->evtmask[src / 32]; in unmask_megamod()
82 raw_spin_lock(&pic->lock); in unmask_megamod()
84 raw_spin_unlock(&pic->lock); in unmask_megamod()
103 pic = cascade->pic; in megamod_irq_cascade()
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/kernel/linux/linux-6.6/sound/soc/codecs/
Dlpass-tx-macro.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
12 #include <sound/soc-dapm.h>
15 #include <linux/clk-provider.h>
17 #include "lpass-macro-common.h"
20 #define CDC_TX_MCLK_EN_MASK BIT(0)
21 #define CDC_TX_MCLK_ENABLE BIT(0)
23 #define CDC_TX_FS_CNT_EN_MASK BIT(0)
24 #define CDC_TX_FS_CNT_ENABLE BIT(0)
26 #define CDC_TX_SWR_RESET_MASK BIT(1)
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/kernel/linux/linux-6.6/sound/soc/sunxi/
Dsun8i-codec.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * (C) Copyright 2010-2016
9 * Mylène Josserand <mylene.josserand@free-electrons.com>
23 #include <sound/soc-dapm.h>
200 regcache_cache_only(scodec->regmap, false); in sun8i_codec_runtime_resume()
202 ret = regcache_sync(scodec->regmap); in sun8i_codec_runtime_resume()
215 regcache_cache_only(scodec->regmap, true); in sun8i_codec_runtime_suspend()
216 regcache_mark_dirty(scodec->regmap); in sun8i_codec_runtime_suspend()
252 return -EINVAL; in sun8i_codec_get_hw_rate()
262 struct sun8i_codec_aif *aif = &scodec->aifs[i]; in sun8i_codec_update_sample_rate()
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/kernel/linux/linux-5.10/sound/soc/codecs/
Dwcd9335.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
3 // Copyright (c) 2017-2018, Linaro Limited
18 #include <sound/soc-dapm.h>
25 #include "wcd-clsh-v2.h"
96 #define WCD9335_CALCULATE_VOUT_D(req_mv) (((req_mv - 650) * 10) / 25)
123 {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \
124 {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \
125 {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \
126 {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"}, \
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