bt1\-ccu\-axi (full) in projects: kernel

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Searched +full:bt1 +full:- +full:ccu +full:- +full:axi (Results 1 – 10 of 10) sorted by relevance

/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
D	baikal,bt1-ccu-div.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: Baikal-T1 Clock Control Unit Dividers 11 - Serge Semin <fancer.lancer@gmail.com> 14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller 15 responsible for the chip subsystems clocking and resetting. The CCU is 18 IP-blocks or to groups of blocks (clock domains). The transformation is done 19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The [all …]
D	baikal,bt1-ccu-pll.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: Baikal-T1 Clock Control Unit PLL 11 - Serge Semin <fancer.lancer@gmail.com> 14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller 15 responsible for the chip subsystems clocking and resetting. The CCU is 18 IP-blocks or to groups of blocks (clock domains). The transformation is done 19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU. [all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
D	baikal,bt1-ccu-div.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: Baikal-T1 Clock Control Unit Dividers 11 - Serge Semin <fancer.lancer@gmail.com> 14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller 15 responsible for the chip subsystems clocking and resetting. The CCU is 18 IP-blocks or to groups of blocks (clock domains). The transformation is done 19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The [all …]
D	baikal,bt1-ccu-pll.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: Baikal-T1 Clock Control Unit PLL 11 - Serge Semin <fancer.lancer@gmail.com> 14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller 15 responsible for the chip subsystems clocking and resetting. The CCU is 18 IP-blocks or to groups of blocks (clock domains). The transformation is done 19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU. [all …]
/kernel/linux/linux-6.6/drivers/clk/baikal-t1/
D	clk-ccu-div.c	`1 // SPDX-License-Identifier: GPL-2.0-only 9 * Baikal-T1 CCU Dividers clock driver 12 #define pr_fmt(fmt) "bt1-ccu-div: " fmt 18 #include <linux/clk-provider.h> 19 #include <linux/reset-controller.h> 26 #include <dt-bindings/clock/bt1-ccu.h> 28 #include "ccu-div.h" 29 #include "ccu-rst.h" 124 * AXI Main Interconnect (axi_main_clk) and DDR AXI-bus (axi_ddr_clk) clocks 127 * the later is clocking the AXI-bus between DDR controller and the Main [all …]`
D	ccu-rst.c	1 // SPDX-License-Identifier: GPL-2.0-only 8 * Baikal-T1 CCU Resets interface driver 11 #define pr_fmt(fmt) "bt1-ccu-rst: " fmt 19 #include <linux/reset-controller.h> 22 #include <dt-bindings/reset/bt1-ccu.h> 24 #include "ccu-rst.h" 66 * Each AXI-bus clock divider is equipped with the corresponding clock-consumer 67 * domain reset (it's self-deasserted reset control). 84 * SATA reference clock domain and APB-bus domain are connected with the 85 * sefl-deasserted reset control, which can be activated via the corresponding [all …]
D	clk-ccu-pll.c	1 // SPDX-License-Identifier: GPL-2.0-only 9 * Baikal-T1 CCU PLL clocks driver 12 #define pr_fmt(fmt) "bt1-ccu-pll: " fmt 18 #include <linux/clk-provider.h> 25 #include <dt-bindings/clock/bt1-ccu.h> 27 #include "ccu-pll.h" 59 * shouldn't be ever gated. SATA and PCIe PLLs are the parents of APB-bus and 60 * DDR controller AXI-bus clocks. If they are gated the system will be 62 * of the corresponding subsystems. So until we aren't ready to re-initialize 93 return data->plls[idx]; in ccu_pll_find_desc() [all …]
/kernel/linux/linux-5.10/drivers/clk/baikal-t1/
D	clk-ccu-div.c	`1 // SPDX-License-Identifier: GPL-2.0-only 9 * Baikal-T1 CCU Dividers clock driver 12 #define pr_fmt(fmt) "bt1-ccu-div: " fmt 17 #include <linux/clk-provider.h> 18 #include <linux/reset-controller.h> 26 #include <dt-bindings/clock/bt1-ccu.h> 27 #include <dt-bindings/reset/bt1-ccu.h> 29 #include "ccu-div.h" 138 * AXI Main Interconnect (axi_main_clk) and DDR AXI-bus (axi_ddr_clk) clocks 141 * the later is clocking the AXI-bus between DDR controller and the Main [all …]`
D	clk-ccu-pll.c	1 // SPDX-License-Identifier: GPL-2.0-only 9 * Baikal-T1 CCU PLL clocks driver 12 #define pr_fmt(fmt) "bt1-ccu-pll: " fmt 17 #include <linux/clk-provider.h> 24 #include <dt-bindings/clock/bt1-ccu.h> 26 #include "ccu-pll.h" 56 * shouldn't be ever gated. SATA and PCIe PLLs are the parents of APB-bus and 57 * DDR controller AXI-bus clocks. If they are gated the system will be 59 * of the corresponding subsystems. So until we aren't ready to re-initialize 88 pll = data->plls[idx]; in ccu_pll_find_desc() [all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/
D	baikal,bt1-pcie.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/baikal,bt1-pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Baikal-T1 PCIe Root Port Controller 10 - Serge Semin <fancer.lancer@gmail.com> 13 Embedded into Baikal-T1 SoC Root Complex controller with a single port 14 activated. It's based on the DWC RC PCIe v4.60a IP-core, which is configured 18 performed by software. There four in- and four outbound iATU regions 22 - $ref: /schemas/pci/snps,dw-pcie.yaml# [all …]