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/kernel/linux/linux-6.6/drivers/media/platform/via/
Dvia-camera.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #define VCR_IC_ACTBUF 0x0018 /* Active video buffer */
13 #define VCR_IC_INTEN 0x0100 /* End of active video int. enable */
14 #define VCR_IC_VBIINT 0x0200 /* End of VBI int enable */
15 #define VCR_IC_VBIBUF 0x0400 /* Current VBI buffer */
18 #define VCR_TSC_ENABLE 0x000001 /* Transport stream input enable */
20 #define VCR_TSC_METHOD 0x00000c /* DMA method (non-functional) */
22 #define VCR_TSC_CBMODE 0x080000 /* Change buffer by byte count */
28 #define VCR_CI_ENABLE 0x00000001 /* Capture enable */
31 #define VCR_CI_VIPEN 0x00000008 /* VIP enable */
[all …]
/kernel/linux/linux-5.10/drivers/media/platform/
Dvia-camera.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #define VCR_IC_ACTBUF 0x0018 /* Active video buffer */
13 #define VCR_IC_INTEN 0x0100 /* End of active video int. enable */
14 #define VCR_IC_VBIINT 0x0200 /* End of VBI int enable */
15 #define VCR_IC_VBIBUF 0x0400 /* Current VBI buffer */
18 #define VCR_TSC_ENABLE 0x000001 /* Transport stream input enable */
20 #define VCR_TSC_METHOD 0x00000c /* DMA method (non-functional) */
22 #define VCR_TSC_CBMODE 0x080000 /* Change buffer by byte count */
28 #define VCR_CI_ENABLE 0x00000001 /* Capture enable */
31 #define VCR_CI_VIPEN 0x00000008 /* VIP enable */
[all …]
/kernel/linux/linux-5.10/include/linux/usb/
Dr8a66597.h1 // SPDX-License-Identifier: GPL-2.0
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
138 #define XTAL 0xC000 /* b15-14: Crystal selection */
142 #define XCKE 0x2000 /* b13: External clock enable */
144 #define SCKE 0x0400 /* b10: USB clock enable */
147 #define HSE 0x0080 /* b7: Hi-speed enable */
149 #define DRPD 0x0020 /* b5: D+/- pull down control */
151 #define USBE 0x0001 /* b0: USB module operation enable */
154 #define OVCBIT 0x8000 /* b15-14: Over-current bit */
155 #define OVCMON 0xC000 /* b15-14: Over-current monitor */
[all …]
/kernel/linux/linux-6.6/include/linux/usb/
Dr8a66597.h1 // SPDX-License-Identifier: GPL-2.0
124 #define XTAL 0xC000 /* b15-14: Crystal selection */
128 #define XCKE 0x2000 /* b13: External clock enable */
130 #define SCKE 0x0400 /* b10: USB clock enable */
133 #define HSE 0x0080 /* b7: Hi-speed enable */
135 #define DRPD 0x0020 /* b5: D+/- pull down control */
137 #define USBE 0x0001 /* b0: USB module operation enable */
140 #define OVCBIT 0x8000 /* b15-14: Over-current bit */
141 #define OVCMON 0xC000 /* b15-14: Over-current monitor */
143 #define IDMON 0x0004 /* b3: ID-pin monitor */
[all …]
/kernel/linux/linux-6.6/drivers/media/platform/st/sti/delta/
Ddelta-mjpeg-fw.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 * @display_luma_p: address of the luma buffer
17 * @display_chroma_p: address of the chroma buffer
31 * @display_luma_p: address of the luma buffer
32 * @display_chroma_p: address of the chroma buffer
33 * @display_decimated_luma_p: address of the decimated luma buffer
34 * @display_decimated_chroma_p: address of the decimated chroma buffer
49 /* enable decimated (for display) reconstruction */
51 /* enable main (for display) reconstruction */
53 /* enable both main & decimated (for display) reconstruction */
[all …]
/kernel/linux/linux-5.10/drivers/media/platform/sti/delta/
Ddelta-mjpeg-fw.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 * @display_luma_p: address of the luma buffer
17 * @display_chroma_p: address of the chroma buffer
31 * @display_luma_p: address of the luma buffer
32 * @display_chroma_p: address of the chroma buffer
33 * @display_decimated_luma_p: address of the decimated luma buffer
34 * @display_decimated_chroma_p: address of the decimated chroma buffer
49 /* enable decimated (for display) reconstruction */
51 /* enable main (for display) reconstruction */
53 /* enable both main & decimated (for display) reconstruction */
[all …]
/kernel/linux/linux-5.10/drivers/media/rc/
Dene_ir.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #define ENE_STATUS 0 /* hardware status - unused */
18 #define ENE_FW_SAMPLE_BUFFER 0xF8F0 /* sample buffer */
24 #define ENE_FW1_ENABLE 0x01 /* enable fw processing */
26 #define ENE_FW1_HAS_EXTRA_BUF 0x04 /* fw uses extra buffer*/
27 #define ENE_FW1_EXTRA_BUF_HND 0x08 /* extra buffer handshake bit*/
30 #define ENE_FW1_WPATTERN 0x20 /* enable wake pattern */
31 #define ENE_FW1_WAKE 0x40 /* enable wake from S3 */
32 #define ENE_FW1_IRQ 0x80 /* enable interrupt */
36 #define ENE_FW2_BUF_WPTR 0x01 /* which half of the buffer to read */
[all …]
/kernel/linux/linux-6.6/drivers/media/rc/
Dene_ir.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #define ENE_STATUS 0 /* hardware status - unused */
18 #define ENE_FW_SAMPLE_BUFFER 0xF8F0 /* sample buffer */
24 #define ENE_FW1_ENABLE 0x01 /* enable fw processing */
26 #define ENE_FW1_HAS_EXTRA_BUF 0x04 /* fw uses extra buffer*/
27 #define ENE_FW1_EXTRA_BUF_HND 0x08 /* extra buffer handshake bit*/
30 #define ENE_FW1_WPATTERN 0x20 /* enable wake pattern */
31 #define ENE_FW1_WAKE 0x40 /* enable wake from S3 */
32 #define ENE_FW1_IRQ 0x80 /* enable interrupt */
36 #define ENE_FW2_BUF_WPTR 0x01 /* which half of the buffer to read */
[all …]
/kernel/linux/linux-6.6/drivers/usb/renesas_usbhs/
Dcommon.h1 /* SPDX-License-Identifier: GPL-1.0+ */
100 #define D2FIFOSEL 0x00F0 /* for R-Car Gen2 */
101 #define D2FIFOCTR 0x00F2 /* for R-Car Gen2 */
102 #define D3FIFOSEL 0x00F4 /* for R-Car Gen2 */
103 #define D3FIFOCTR 0x00F6 /* for R-Car Gen2 */
107 #define SCKE (1 << 10) /* USB Module Clock Enable */
108 #define CNEN (1 << 8) /* Single-ended receiver operation Enable */
109 #define HSE (1 << 7) /* High-Speed Operation Enable */
111 #define DRPD (1 << 5) /* D+ Line/D- Line Resistance Control */
113 #define USBE (1 << 0) /* USB Module Operation Enable */
[all …]
/kernel/linux/linux-5.10/drivers/usb/renesas_usbhs/
Dcommon.h1 /* SPDX-License-Identifier: GPL-1.0+ */
100 #define D2FIFOSEL 0x00F0 /* for R-Car Gen2 */
101 #define D2FIFOCTR 0x00F2 /* for R-Car Gen2 */
102 #define D3FIFOSEL 0x00F4 /* for R-Car Gen2 */
103 #define D3FIFOCTR 0x00F6 /* for R-Car Gen2 */
107 #define SCKE (1 << 10) /* USB Module Clock Enable */
108 #define CNEN (1 << 8) /* Single-ended receiver operation Enable */
109 #define HSE (1 << 7) /* High-Speed Operation Enable */
111 #define DRPD (1 << 5) /* D+ Line/D- Line Resistance Control */
113 #define USBE (1 << 0) /* USB Module Operation Enable */
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/
Di915_mitigations.c1 // SPDX-License-Identifier: MIT
41 return -ENOMEM; in mitigations_set()
44 bool enable = true; in mitigations_set() local
62 enable = !enable; in mitigations_set()
67 enable = !enable; in mitigations_set()
76 if (enable) in mitigations_set()
86 err = -EINVAL; in mitigations_set()
98 static int mitigations_get(char *buffer, const struct kernel_param *kp) in mitigations_get() argument
102 bool enable; in mitigations_get() local
105 return scnprintf(buffer, PAGE_SIZE, "%s\n", "off"); in mitigations_get()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/
Di915_mitigations.c1 // SPDX-License-Identifier: MIT
40 return -ENOMEM; in mitigations_set()
43 bool enable = true; in mitigations_set() local
61 enable = !enable; in mitigations_set()
66 enable = !enable; in mitigations_set()
75 if (enable) in mitigations_set()
85 err = -EINVAL; in mitigations_set()
97 static int mitigations_get(char *buffer, const struct kernel_param *kp) in mitigations_get() argument
101 bool enable; in mitigations_get() local
104 return scnprintf(buffer, PAGE_SIZE, "%s\n", "off"); in mitigations_get()
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/aquantia/atlantic/hw_atl/
Dhw_atl_llh.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2014-2019 aQuantia Corporation
5 * Copyright (C) 2019-2020 Marvell International Ltd.
119 /* set interrupt mapping enable rx */
123 /* set interrupt mapping enable tx */
157 void hw_atl_itr_rsc_en_set(struct aq_hw_s *aq_hw, u32 enable);
167 /* set rx dca enable */
173 /* set rx descriptor data buffer size */
178 /* set rx descriptor dca enable */
182 /* set rx descriptor enable */
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/aquantia/atlantic/hw_atl/
Dhw_atl_llh.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2014-2019 aQuantia Corporation
5 * Copyright (C) 2019-2020 Marvell International Ltd.
119 /* set interrupt mapping enable rx */
123 /* set interrupt mapping enable tx */
157 void hw_atl_itr_rsc_en_set(struct aq_hw_s *aq_hw, u32 enable);
167 /* set rx dca enable */
173 /* set rx descriptor data buffer size */
178 /* set rx descriptor dca enable */
182 /* set rx descriptor enable */
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
Dih_v6_1.c40 * ih_v6_1_init_register_offset - Initialize register offset for ih rings
52 if (adev->irq.ih.ring_size) { in ih_v6_1_init_register_offset()
53 ih_regs = &adev->irq.ih.ih_regs; in ih_v6_1_init_register_offset()
54 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE); in ih_v6_1_init_register_offset()
55 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI); in ih_v6_1_init_register_offset()
56 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL); in ih_v6_1_init_register_offset()
57 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR); in ih_v6_1_init_register_offset()
58 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR); in ih_v6_1_init_register_offset()
59 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_DOORBELL_RPTR); in ih_v6_1_init_register_offset()
60 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_ADDR_LO); in ih_v6_1_init_register_offset()
[all …]
Dvega10_ih.c41 * vega10_ih_init_register_offset - Initialize register offset for ih rings
51 if (adev->irq.ih.ring_size) { in vega10_ih_init_register_offset()
52 ih_regs = &adev->irq.ih.ih_regs; in vega10_ih_init_register_offset()
53 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); in vega10_ih_init_register_offset()
54 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); in vega10_ih_init_register_offset()
55 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); in vega10_ih_init_register_offset()
56 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); in vega10_ih_init_register_offset()
57 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); in vega10_ih_init_register_offset()
58 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); in vega10_ih_init_register_offset()
59 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); in vega10_ih_init_register_offset()
[all …]
Dnavi10_ih.c43 * navi10_ih_init_register_offset - Initialize register offset for ih rings
53 if (adev->irq.ih.ring_size) { in navi10_ih_init_register_offset()
54 ih_regs = &adev->irq.ih.ih_regs; in navi10_ih_init_register_offset()
55 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); in navi10_ih_init_register_offset()
56 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); in navi10_ih_init_register_offset()
57 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); in navi10_ih_init_register_offset()
58 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); in navi10_ih_init_register_offset()
59 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); in navi10_ih_init_register_offset()
60 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); in navi10_ih_init_register_offset()
61 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); in navi10_ih_init_register_offset()
[all …]
Dvega20_ih.c49 * vega20_ih_init_register_offset - Initialize register offset for ih rings
59 if (adev->irq.ih.ring_size) { in vega20_ih_init_register_offset()
60 ih_regs = &adev->irq.ih.ih_regs; in vega20_ih_init_register_offset()
61 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); in vega20_ih_init_register_offset()
62 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); in vega20_ih_init_register_offset()
63 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); in vega20_ih_init_register_offset()
64 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); in vega20_ih_init_register_offset()
65 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); in vega20_ih_init_register_offset()
66 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); in vega20_ih_init_register_offset()
67 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); in vega20_ih_init_register_offset()
[all …]
Dih_v6_0.c40 * ih_v6_0_init_register_offset - Initialize register offset for ih rings
52 if (adev->irq.ih.ring_size) { in ih_v6_0_init_register_offset()
53 ih_regs = &adev->irq.ih.ih_regs; in ih_v6_0_init_register_offset()
54 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE); in ih_v6_0_init_register_offset()
55 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI); in ih_v6_0_init_register_offset()
56 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL); in ih_v6_0_init_register_offset()
57 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR); in ih_v6_0_init_register_offset()
58 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR); in ih_v6_0_init_register_offset()
59 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_DOORBELL_RPTR); in ih_v6_0_init_register_offset()
60 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_ADDR_LO); in ih_v6_0_init_register_offset()
[all …]
/kernel/linux/linux-6.6/drivers/net/wan/
Dhd64570.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 /* SCA HD64570 register definitions - all addresses for mode 0 (8086 MPU)
24 #define DMER 0x09 /* DMA Master Enable */
32 #define IER0 0x14 /* Interrupt Enable 0 */
33 #define IER1 0x15 /* Interrupt Enable 1 */
34 #define IER2 0x16 /* Interrupt Enable 2 */
42 /* MSCI channel (port) 0 registers - offset 0x20
43 MSCI channel (port) 1 registers - offset 0x40 */
48 #define TRBL 0x00 /* TX/RX buffer L */
49 #define TRBH 0x01 /* TX/RX buffer H */
[all …]
/kernel/linux/linux-5.10/drivers/net/wan/
Dhd64570.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 /* SCA HD64570 register definitions - all addresses for mode 0 (8086 MPU)
24 #define DMER 0x09 /* DMA Master Enable */
32 #define IER0 0x14 /* Interrupt Enable 0 */
33 #define IER1 0x15 /* Interrupt Enable 1 */
34 #define IER2 0x16 /* Interrupt Enable 2 */
42 /* MSCI channel (port) 0 registers - offset 0x20
43 MSCI channel (port) 1 registers - offset 0x40 */
48 #define TRBL 0x00 /* TX/RX buffer L */
49 #define TRBH 0x01 /* TX/RX buffer H */
[all …]
/kernel/linux/linux-6.6/drivers/pci/
Dvc.c1 // SPDX-License-Identifier: GPL-2.0
19 * pci_vc_save_restore_dwords - Save or restore a series of dwords
22 * @buf: buffer to save to or restore from
40 * pci_vc_load_arb_table - load and wait for VC arbitration table
63 * pci_vc_load_port_arb_table - Load and wait for VC port arbitration table
66 * @res: VC resource number, ie. VCn (0-7)
91 * pci_vc_enable - Enable virtual channel
94 * @res: VC res number, ie. VCn (0-7)
96 * A VC is enabled by setting the enable bit in matching resource control
98 * end of the link. To keep this simple we enable from the downstream device.
[all …]
/kernel/linux/linux-5.10/drivers/pci/
Dvc.c1 // SPDX-License-Identifier: GPL-2.0
19 * pci_vc_save_restore_dwords - Save or restore a series of dwords
22 * @buf: buffer to save to or restore from
40 * pci_vc_load_arb_table - load and wait for VC arbitration table
63 * pci_vc_load_port_arb_table - Load and wait for VC port arbitration table
66 * @res: VC resource number, ie. VCn (0-7)
91 * pci_vc_enable - Enable virtual channel
94 * @res: VC res number, ie. VCn (0-7)
96 * A VC is enabled by setting the enable bit in matching resource control
98 * end of the link. To keep this simple we enable from the downstream device.
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/intel/ixgbe/
Dixgbe_dcb_82598.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
10 #define IXGBE_DPMCS_TDPAC 0x00000001 /* 0 Round Robin, 1 DFP - Deficit Fixed Priority */
15 #define IXGBE_RUPPBMR_MQA 0x80000000 /* Enable UP to queue mapping */
18 #define IXGBE_RT2CR_LSP 0x80000000 /* LSP enable bit */
20 #define IXGBE_RDRXCTL_MPBEN 0x00000010 /* DMA config for multiple packet buffers enable */
21 #define IXGBE_RDRXCTL_MCEN 0x00000040 /* DMA config for multiple cores (RSS) enable */
33 #define IXGBE_PDPMCS_TPPAC 0x00000020 /* 0 Round Robin, 1 for DFP - Deficit Fixed Priority */
35 #define IXGBE_PDPMCS_TRM 0x00000100 /* Transmit Recycle Mode enable */
37 #define IXGBE_DTXCTL_ENDBUBD 0x00000004 /* Enable DBU buffer division */
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/intel/ixgbe/
Dixgbe_dcb_82598.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
10 #define IXGBE_DPMCS_TDPAC 0x00000001 /* 0 Round Robin, 1 DFP - Deficit Fixed Priority */
15 #define IXGBE_RUPPBMR_MQA 0x80000000 /* Enable UP to queue mapping */
18 #define IXGBE_RT2CR_LSP 0x80000000 /* LSP enable bit */
20 #define IXGBE_RDRXCTL_MPBEN 0x00000010 /* DMA config for multiple packet buffers enable */
21 #define IXGBE_RDRXCTL_MCEN 0x00000040 /* DMA config for multiple cores (RSS) enable */
33 #define IXGBE_PDPMCS_TPPAC 0x00000020 /* 0 Round Robin, 1 for DFP - Deficit Fixed Priority */
35 #define IXGBE_PDPMCS_TRM 0x00000100 /* Transmit Recycle Mode enable */
37 #define IXGBE_DTXCTL_ENDBUBD 0x00000004 /* Enable DBU buffer division */
[all …]

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