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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/exynos/
Dexynos_dsim.txt4 - compatible: value should be one of the following
5 "samsung,exynos3250-mipi-dsi" /* for Exynos3250/3472 SoCs */
6 "samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */
7 "samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */
8 "samsung,exynos5422-mipi-dsi" /* for Exynos5422/5800 SoCs */
9 "samsung,exynos5433-mipi-dsi" /* for Exynos5433 SoCs */
10 - reg: physical base address and length of the registers set for the device
11 - interrupts: should contain DSI interrupt
12 - clocks: list of clock specifiers, must contain an entry for each required
13 entry in clock-names
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/bridge/
Dsamsung,mipi-dsim.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inki Dae <inki.dae@samsung.com>
11 - Jagan Teki <jagan@amarulasolutions.com>
12 - Marek Szyprowski <m.szyprowski@samsung.com>
21 - enum:
22 - samsung,exynos3250-mipi-dsi
23 - samsung,exynos4210-mipi-dsi
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/
Dimx8dxl-ss-conn.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 /delete-node/ &enet1_lpcg;
7 /delete-node/ &fec2;
10 conn_enet0_root_clk: clock-conn-enet0-root {
11 compatible = "fixed-clock";
12 #clock-cells = <0>;
13 clock-frequency = <250000000>;
14 clock-output-names = "conn_enet0_root_clk";
18 compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a";
20 interrupt-parent = <&gic>;
[all …]
Dimx8-ss-conn.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
11 compatible = "simple-bus";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 conn_axi_clk: clock-conn-axi {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
[all …]
Dimx8mm-venice-gw72xx-0x-rpidsi.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
8 #include "imx8mm-pinfunc.h"
10 /dts-v1/;
14 compatible = "gw,imx8mm-gw73xx-0x", "fsl,imx8mm";
17 compatible = "powertip,ph800480t013-idf02";
18 power-supply = <&attiny>;
23 remote-endpoint = <&bridge_out>;
30 #address-cells = <1>;
31 #size-cells = <0>;
[all …]
Dimx8mm-venice-gw73xx-0x-rpidsi.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
8 #include "imx8mm-pinfunc.h"
10 /dts-v1/;
14 compatible = "gw,imx8mm-gw73xx-0x", "fsl,imx8mm";
17 compatible = "powertip,ph800480t013-idf02";
18 power-supply = <&attiny>;
23 remote-endpoint = <&bridge_out>;
30 #address-cells = <1>;
31 #size-cells = <0>;
[all …]
Dimx8mp-venice-gw74xx-rpidsi.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 compatible = "gateworks,imx8mp-gw74xx", "fsl,imx8mp";
13 compatible = "powertip,ph800480t013-idf02";
14 power-supply = <&attiny>;
19 remote-endpoint = <&bridge_out>;
26 #address-cells = <1>;
27 #size-cells = <0>;
30 compatible = "raspberrypi,7inch-touchscreen-panel-regulator";
40 samsung,burst-clock-frequency = <891000000>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Domap2420-n8x0-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
11 stdout-path = &uart3;
16 compatible = "i2c-cbus-gpio";
21 #address-cells = <1>;
22 #size-cells = <0>;
25 interrupt-parent = <&gpio4>;
34 clock-frequency = <400000>;
44 clock-frequency = <400000>;
50 /* gpio-irq for dma: 26 */
53 #address-cells = <1>;
[all …]
Dimx7ulp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
8 #include <dt-bindings/clock/imx7ulp-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "imx7ulp-pinfunc.h"
15 interrupt-parent = <&intc>;
17 #address-cells = <1>;
18 #size-cells = <1>;
37 #address-cells = <1>;
[all …]
Domap3-n950-n9.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap3-n950-n9.dtsi - Device Tree file for Nokia N950 & N9 (common stuff)
13 cpu0-supply = <&vcc>;
23 compatible = "regulator-fixed";
24 regulator-name = "VEMMC";
25 regulator-min-microvolt = <2900000>;
26 regulator-max-microvolt = <2900000>;
28 startup-delay-us = <150>;
29 enable-active-high;
33 compatible = "regulator-fixed";
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/ti/omap/
Domap2420-n8x0-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
11 stdout-path = &uart3;
16 compatible = "i2c-cbus-gpio";
21 #address-cells = <1>;
22 #size-cells = <0>;
25 interrupt-parent = <&gpio4>;
34 clock-frequency = <400000>;
44 clock-frequency = <400000>;
50 /* gpio-irq for dma: 26 */
53 #address-cells = <1>;
[all …]
Domap3-n950-n9.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap3-n950-n9.dtsi - Device Tree file for Nokia N950 & N9 (common stuff)
13 cpu0-supply = <&vcc>;
23 compatible = "regulator-fixed";
24 regulator-name = "VEMMC";
25 regulator-min-microvolt = <2900000>;
26 regulator-max-microvolt = <2900000>;
28 startup-delay-us = <150>;
29 enable-active-high;
33 compatible = "regulator-fixed";
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/xilinx/
Dzynqmp-zc1751-xm017-dc3.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm017-dc3
5 * (C) Copyright 2016 - 2021, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/phy/phy.h>
17 model = "ZynqMP zc1751-xm017-dc3 RevA";
18 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
34 stdout-path = "serial0:115200n8";
43 compatible = "fixed-clock";
[all …]
Dzynqmp-sck-kv-g-revA.dtso1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
9 * "A" - A01 board un-modified (NXP)
10 * "Y" - A01 board modified with legacy interposer (Nexperia)
11 * "Z" - A01 board modified with Diode interposer
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/net/ti-dp83867.h>
18 #include <dt-bindings/phy/phy.h>
19 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
[all …]
Dzynqmp-zc1751-xm015-dc1.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 model = "ZynqMP zc1751-xm015-dc1 RevA";
[all …]
/kernel/linux/linux-5.10/include/sound/
Dak4117.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #define AK4117_REG_CLOCK 0x01 /* clock control */
23 #define AK4117_REG_Pc0 0x0d /* burst preamble Pc byte 0 */
24 #define AK4117_REG_Pc1 0x0e /* burst preamble Pc byte 1 */
25 #define AK4117_REG_Pd0 0x0f /* burst preamble Pd byte 0 */
26 #define AK4117_REG_Pd1 0x10 /* burst preamble Pd byte 1 */
27 #define AK4117_REG_QSUB_ADDR 0x11 /* Q-subcode address + control */
28 #define AK4117_REG_QSUB_TRACK 0x12 /* Q-subcode track */
29 #define AK4117_REG_QSUB_INDEX 0x13 /* Q-subcode index */
30 #define AK4117_REG_QSUB_MINUTE 0x14 /* Q-subcode minute */
[all …]
Dak4114.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
29 #define AK4114_REG_Pc0 0x12 /* burst preamble Pc byte 0 */
30 #define AK4114_REG_Pc1 0x13 /* burst preamble Pc byte 1 */
31 #define AK4114_REG_Pd0 0x14 /* burst preamble Pd byte 0 */
32 #define AK4114_REG_Pd1 0x15 /* burst preamble Pd byte 1 */
33 #define AK4114_REG_QSUB_ADDR 0x16 /* Q-subcode address + control */
34 #define AK4114_REG_QSUB_TRACK 0x17 /* Q-subcode track */
35 #define AK4114_REG_QSUB_INDEX 0x18 /* Q-subcode index */
36 #define AK4114_REG_QSUB_MINUTE 0x19 /* Q-subcode minute */
37 #define AK4114_REG_QSUB_SECOND 0x1a /* Q-subcode second */
[all …]
Dak4113.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
42 /* burst preamble Pc byte 0 */
44 /* burst preamble Pc byte 1 */
46 /* burst preamble Pd byte 0 */
48 /* burst preamble Pd byte 1 */
50 /* Q-subcode address + control */
52 /* Q-subcode track */
54 /* Q-subcode index */
56 /* Q-subcode minute */
58 /* Q-subcode second */
[all …]
/kernel/linux/linux-6.6/include/sound/
Dak4117.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #define AK4117_REG_CLOCK 0x01 /* clock control */
23 #define AK4117_REG_Pc0 0x0d /* burst preamble Pc byte 0 */
24 #define AK4117_REG_Pc1 0x0e /* burst preamble Pc byte 1 */
25 #define AK4117_REG_Pd0 0x0f /* burst preamble Pd byte 0 */
26 #define AK4117_REG_Pd1 0x10 /* burst preamble Pd byte 1 */
27 #define AK4117_REG_QSUB_ADDR 0x11 /* Q-subcode address + control */
28 #define AK4117_REG_QSUB_TRACK 0x12 /* Q-subcode track */
29 #define AK4117_REG_QSUB_INDEX 0x13 /* Q-subcode index */
30 #define AK4117_REG_QSUB_MINUTE 0x14 /* Q-subcode minute */
[all …]
Dak4114.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
29 #define AK4114_REG_Pc0 0x12 /* burst preamble Pc byte 0 */
30 #define AK4114_REG_Pc1 0x13 /* burst preamble Pc byte 1 */
31 #define AK4114_REG_Pd0 0x14 /* burst preamble Pd byte 0 */
32 #define AK4114_REG_Pd1 0x15 /* burst preamble Pd byte 1 */
33 #define AK4114_REG_QSUB_ADDR 0x16 /* Q-subcode address + control */
34 #define AK4114_REG_QSUB_TRACK 0x17 /* Q-subcode track */
35 #define AK4114_REG_QSUB_INDEX 0x18 /* Q-subcode index */
36 #define AK4114_REG_QSUB_MINUTE 0x19 /* Q-subcode minute */
37 #define AK4114_REG_QSUB_SECOND 0x1a /* Q-subcode second */
[all …]
Dak4113.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
42 /* burst preamble Pc byte 0 */
44 /* burst preamble Pc byte 1 */
46 /* burst preamble Pd byte 0 */
48 /* burst preamble Pd byte 1 */
50 /* Q-subcode address + control */
52 /* Q-subcode track */
54 /* Q-subcode index */
56 /* Q-subcode minute */
58 /* Q-subcode second */
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/tilcdc/
Dpanel.txt1 Device-Tree bindings for tilcdc DRM generic panel output driver
4 - compatible: value should be "ti,tilcdc,panel".
5 - panel-info: configuration info to configure LCDC correctly for the panel
6 - ac-bias: AC Bias Pin Frequency
7 - ac-bias-intrpt: AC Bias Pin Transitions per Interrupt
8 - dma-burst-sz: DMA burst size
9 - bpp: Bits per pixel
10 - fdd: FIFO DMA Request Delay
11 - sync-edge: Horizontal and Vertical Sync Edge: 0=rising 1=falling
12 - sync-ctrl: Horizontal and Vertical Sync: Control: 0=ignore
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/tilcdc/
Dpanel.txt1 Device-Tree bindings for tilcdc DRM generic panel output driver
4 - compatible: value should be "ti,tilcdc,panel".
5 - panel-info: configuration info to configure LCDC correctly for the panel
6 - ac-bias: AC Bias Pin Frequency
7 - ac-bias-intrpt: AC Bias Pin Transitions per Interrupt
8 - dma-burst-sz: DMA burst size
9 - bpp: Bits per pixel
10 - fdd: FIFO DMA Request Delay
11 - sync-edge: Horizontal and Vertical Sync Edge: 0=rising 1=falling
12 - sync-ctrl: Horizontal and Vertical Sync: Control: 0=ignore
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/xilinx/
Dzynqmp-zc1751-xm017-dc3.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm017-dc3
5 * (C) Copyright 2016 - 2019, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
16 model = "ZynqMP zc1751-xm017-dc3 RevA";
17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
31 stdout-path = "serial0:115200n8";
74 phy-handle = <&phy0>;
75 phy-mode = "rgmii-id";
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/imx/
Dimx7ulp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
8 #include <dt-bindings/clock/imx7ulp-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "imx7ulp-pinfunc.h"
15 interrupt-parent = <&intc>;
17 #address-cells = <1>;
18 #size-cells = <1>;
37 #address-cells = <1>;
[all …]

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