| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/s390/cf_z16/ |
| D | extended.json | 3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been up…
10 "Unit": "CPU-M-CF",
14 …nslation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This is a r…
17 "Unit": "CPU-M-CF",
21 …s for a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in progress…
24 "Unit": "CPU-M-CF",
28 …en into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte pa…
31 "Unit": "CPU-M-CF",
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/ |
| D | cache.json | 111 …tion": "Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetche…
114 …tion": "Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetche…
117 …Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
120 …Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
123 …Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
126 …Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
141 …Level 2 cache write streaming mode. This event counts for each cycle where the core is in write-st…
144 …Level 2 cache write streaming mode. This event counts for each cycle where the core is in write-st…
147 …Level 3 cache write streaming mode. This event counts for each cycle where the core is in write-st…
150 …Level 3 cache write streaming mode. This event counts for each cycle where the core is in write-st…
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/s390/cf_z13/ |
| D | extended.json | 3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been up…
10 "Unit": "CPU-M-CF",
14 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
17 "Unit": "CPU-M-CF",
21 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "DTLB1 One-Megabyte Page Writes",
28 …on": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a …
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/s390/cf_z13/ |
| D | extended.json | 3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been up…
10 "Unit": "CPU-M-CF",
14 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
17 "Unit": "CPU-M-CF",
21 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "DTLB1 One-Megabyte Page Writes",
28 …on": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a …
[all …]
|
| /kernel/linux/linux-5.10/arch/loongarch/boot/dts/loongson/ |
| D | loongson3.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
4 * Loongson-3 may have as many as 4 nodes, each node has 4 cores.
8 #address-cells = <1>;
9 #size-cells = <0>;
15 l2-cache = <&vcache0>;
16 next-level-cache = <&scache0>;
23 l2-cache = <&vcache1>;
24 next-level-cache = <&scache0>;
31 l2-cache = <&vcache2>;
32 next-level-cache = <&scache0>;
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/s390/cf_z14/ |
| D | extended.json | 3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been up…
10 "Unit": "CPU-M-CF",
14 …ranslation Lookaside Buffer 2 (TLB2) and the request was made by the data cache. This is a replace…
17 "Unit": "CPU-M-CF",
21 …ss for a request made by the data cache. Incremented by one for every TLB2 miss in progress for th…
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "DTLB2 One-Megabyte Page Writes",
28 …en into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte pa…
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/s390/cf_z14/ |
| D | extended.json | 3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been up…
10 "Unit": "CPU-M-CF",
14 … written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the data cache"
17 "Unit": "CPU-M-CF",
21 …ss for a request made by the data cache. Incremented by one for every TLB2 miss in progress for th…
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "DTLB2 One-Megabyte Page Writes",
28 …en into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte pa…
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/ |
| D | cache.json | 105 …Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
108 …Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
111 …Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
114 …Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
117 …on": "Level 1 data cache refill due to prefetch. This event counts any linefills from the prefetch…
120 …on": "Level 1 data cache refill due to prefetch. This event counts any linefills from the prefetch…
123 …Level 2 cache write streaming mode. This event counts for each cycle where the core is in write-st…
126 …Level 2 cache write streaming mode. This event counts for each cycle where the core is in write-st…
129 …"PublicDescription": "Level 1 data cache entering write streaming mode.This event counts for each …
132 …"BriefDescription": "Level 1 data cache entering write streaming mode.This event counts for each e…
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/s390/cf_zec12/ |
| D | extended.json | 3 "Unit": "CPU-M-CF",
7 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
10 "Unit": "CPU-M-CF",
14 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
17 "Unit": "CPU-M-CF",
21 … directory write to the Level-1 Data cache directory where the returned cache line was sourced fro…
24 "Unit": "CPU-M-CF",
28 …ectory write to the Level-1 Instruction cache directory where the returned cache line was sourced …
31 "Unit": "CPU-M-CF",
35 … "A directory write to the Level-1 Data cache directory where the returned cache line was sourced …
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/s390/cf_zec12/ |
| D | extended.json | 3 "Unit": "CPU-M-CF",
7 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
10 "Unit": "CPU-M-CF",
14 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
17 "Unit": "CPU-M-CF",
21 … directory write to the Level-1 Data cache directory where the returned cache line was sourced fro…
24 "Unit": "CPU-M-CF",
28 …ectory write to the Level-1 Instruction cache directory where the returned cache line was sourced …
31 "Unit": "CPU-M-CF",
35 … "A directory write to the Level-1 Data cache directory where the returned cache line was sourced …
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/s390/cf_z15/ |
| D | extended.json | 3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been up…
10 "Unit": "CPU-M-CF",
14 … written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the data cache"
17 "Unit": "CPU-M-CF",
21 …ss for a request made by the data cache. Incremented by one for every TLB2 miss in progress for th…
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "DTLB2 One-Megabyte Page Writes",
28 …en into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte pa…
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/s390/cf_z15/ |
| D | extended.json | 3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been up…
10 "Unit": "CPU-M-CF",
14 …ranslation Lookaside Buffer 2 (TLB2) and the request was made by the data cache. This is a replace…
17 "Unit": "CPU-M-CF",
21 …ss for a request made by the data cache. Incremented by one for every TLB2 miss in progress for th…
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "DTLB2 One-Megabyte Page Writes",
28 …en into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte pa…
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/s390/cf_z196/ |
| D | extended.json | 3 "Unit": "CPU-M-CF",
7 …on": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced…
10 "Unit": "CPU-M-CF",
14 …on": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced…
17 "Unit": "CPU-M-CF",
21 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
24 "Unit": "CPU-M-CF",
28 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
31 "Unit": "CPU-M-CF",
35 "PublicDescription": "Incremented by one for every store sent to Level-2 cache"
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/s390/cf_z196/ |
| D | extended.json | 3 "Unit": "CPU-M-CF",
7 …n": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourc…
10 "Unit": "CPU-M-CF",
14 …"A directory write to the Level-1 Instruction Cache directory where the returned cache line was so…
17 "Unit": "CPU-M-CF",
21 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
24 "Unit": "CPU-M-CF",
28 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
31 "Unit": "CPU-M-CF",
35 "PublicDescription": "Incremented by one for every store sent to Level-2 cache."
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/ |
| D | l2_cache.json | 4 …level 2 cache accesses. level 2 cache is a unified cache for data and instruction accesses. Access…
8 …ts cache line refills into the level 2 cache. level 2 cache is a unified cache for data and instru…
12 …-backs of data from the L2 cache to outside the CPU. This includes snoops to the L2 (from other CP…
20 …level 2 cache accesses due to memory read operations. level 2 cache is a unified cache for data an…
24 …level 2 cache accesses due to memory write operations. level 2 cache is a unified cache for data a…
28 …ounted by L2D_CACHE_RD. level 2 cache is a unified cache for data and instruction accesses, access…
32 …ounted by L2D_CACHE_WR. level 2 cache is a unified cache for data and instruction accesses, access…
36 …licDescription": "Counts evictions from the level 2 cache because of a line being allocated into t…
40 …s write-backs from the level 2 cache that are a result of either:\n\n1. Cache maintenance operatio…
44 …cache line in the level 2 cache by cache maintenance operations that operate by a virtual address,…
[all …]
|
| D | l1d_cache.json | 4 …level 1 data cache refills caused by speculatively executed load or store operations that missed i…
8 …level 1 data cache accesses from any load/store operations. Atomic operations that resolve in the …
12 …-backs of dirty data from the L1 data cache to the L2 cache. This occurs when either a dirty cache…
16 …"PublicDescription": "Counts cache line refills into the level 1 data cache from any memory read o…
20 …"PublicDescription": "Counts level 1 data cache accesses from any load operation. Atomic load oper…
24 …ption": "Counts level 1 data cache accesses generated by store operations. This event also counts …
28 …level 1 data cache refills caused by speculatively executed load instructions where the memory rea…
32 …level 1 data cache refills caused by speculatively executed store instructions where the memory wr…
36 …"PublicDescription": "Counts level 1 data cache refills where the cache line data came from caches…
40 …"PublicDescription": "Counts level 1 data cache refills for which the cache line data came from ou…
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/ |
| D | l2_cache.json | 4 …level 2 cache accesses. level 2 cache is a unified cache for data and instruction accesses. Access…
8 …ts cache line refills into the level 2 cache. level 2 cache is a unified cache for data and instru…
12 …-backs of data from the L2 cache to outside the CPU. This includes snoops to the L2 (from other CP…
20 …level 2 cache accesses due to memory read operations. level 2 cache is a unified cache for data an…
24 …level 2 cache accesses due to memory write operations. level 2 cache is a unified cache for data a…
28 …ounted by L2D_CACHE_RD. level 2 cache is a unified cache for data and instruction accesses, access…
32 …ounted by L2D_CACHE_WR. level 2 cache is a unified cache for data and instruction accesses, access…
36 …licDescription": "Counts evictions from the level 2 cache because of a line being allocated into t…
40 …s write-backs from the level 2 cache that are a result of either:\n\n1. Cache maintenance operatio…
44 …cache line in the level 2 cache by cache maintenance operations that operate by a virtual address,…
|
| D | l1d_cache.json | 4 …level 1 data cache refills caused by speculatively executed load or store operations that missed i…
8 …level 1 data cache accesses from any load/store operations. Atomic operations that resolve in the …
12 …-backs of dirty data from the L1 data cache to the L2 cache. This occurs when either a dirty cache…
16 …"PublicDescription": "Counts level 1 data cache accesses from any load operation. Atomic load oper…
20 …ption": "Counts level 1 data cache accesses generated by store operations. This event also counts …
24 …level 1 data cache refills caused by speculatively executed load instructions where the memory rea…
28 …level 1 data cache refills caused by speculatively executed store instructions where the memory wr…
32 …"PublicDescription": "Counts level 1 data cache refills where the cache line data came from caches…
36 …"PublicDescription": "Counts level 1 data cache refills for which the cache line data came from ou…
40 … dirty cache line evictions from the level 1 data cache caused by a new cache line allocation. Thi…
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/s390/cf_z10/ |
| D | extended.json | 3 "Unit": "CPU-M-CF",
7 …: "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced fr…
10 "Unit": "CPU-M-CF",
14 … "A directory write to the Level-1 D-Cache directory where the installed cache line was sourced fr…
17 "Unit": "CPU-M-CF",
21 …Level-1 I-Cache directory where the installed cache line was sourced from the Level-3 cache that i…
24 "Unit": "CPU-M-CF",
28 … Level-1 D-Cache directory where the installtion cache line was source from the Level-3 cache that…
31 "Unit": "CPU-M-CF",
35 …Level-1 I-Cache directory where the installed cache line was sourced from a Level-3 cache that is …
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/s390/cf_z10/ |
| D | extended.json | 3 "Unit": "CPU-M-CF",
7 …directory write to the Level-1 Instruction Cache directory where the returned cache line was sourc…
10 "Unit": "CPU-M-CF",
14 …"A directory write to the Level-1 Data Cache directory where the installed cache line was sourced …
17 "Unit": "CPU-M-CF",
21 …Level-1 Instruction Cache directory where the installed cache line was sourced from the Level-3 ca…
24 "Unit": "CPU-M-CF",
28 …Level-1 Data Cache directory where the installed cache line was source from the Level-3 cache that…
31 "Unit": "CPU-M-CF",
35 …Level-1 Instruction Cache directory where the installed cache line was sourced from a Level-3 cach…
[all …]
|
| /kernel/linux/linux-6.6/arch/powerpc/kernel/ |
| D | cacheinfo.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Processor cache information made available to userspace via sysfs;
26 /* per-cpu object for tracking:
27 * - a "cache" kobject for the top-level directory
28 * - a list of "index" objects representing the cpu's local cache hierarchy
31 struct kobject *kobj; /* bare (not embedded) kobject for cache
36 /* "index" object: each cpu's cache directory has an index
37 * subdirectory corresponding to a cache object associated with the
43 struct cache *cache; member
47 * cache type */
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/arm64/ |
| D | armv8-recommended.json | 3 "PublicDescription": "Attributable Level 1 data cache access, read",
6 "BriefDescription": "L1D cache access, read"
9 "PublicDescription": "Attributable Level 1 data cache access, write",
12 "BriefDescription": "L1D cache access, write"
15 "PublicDescription": "Attributable Level 1 data cache refill, read",
18 "BriefDescription": "L1D cache refill, read"
21 "PublicDescription": "Attributable Level 1 data cache refill, write",
24 "BriefDescription": "L1D cache refill, write"
27 "PublicDescription": "Attributable Level 1 data cache refill, inner",
30 "BriefDescription": "L1D cache refill, inner"
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/arm64/ |
| D | recommended.json | 3 "PublicDescription": "Attributable Level 1 data cache access, read",
6 "BriefDescription": "L1D cache access, read"
9 "PublicDescription": "Attributable Level 1 data cache access, write",
12 "BriefDescription": "L1D cache access, write"
15 "PublicDescription": "Attributable Level 1 data cache refill, read",
18 "BriefDescription": "L1D cache refill, read"
21 "PublicDescription": "Attributable Level 1 data cache refill, write",
24 "BriefDescription": "L1D cache refill, write"
27 "PublicDescription": "Attributable Level 1 data cache refill, inner",
30 "BriefDescription": "L1D cache refill, inner"
[all …]
|
| /kernel/linux/linux-5.10/arch/powerpc/kernel/ |
| D | cacheinfo.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Processor cache information made available to userspace via sysfs;
27 /* per-cpu object for tracking:
28 * - a "cache" kobject for the top-level directory
29 * - a list of "index" objects representing the cpu's local cache hierarchy
32 struct kobject *kobj; /* bare (not embedded) kobject for cache
37 /* "index" object: each cpu's cache directory has an index
38 * subdirectory corresponding to a cache object associated with the
44 struct cache *cache; member
48 * cache type */
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/arm64/ampere/emag/ |
| D | cache.json | 42 "PublicDescription": "Level 1 instruction cache refill",
45 "BriefDescription": "L1I cache refill"
48 "PublicDescription": "Level 1 instruction TLB refill",
54 "PublicDescription": "Level 1 data cache refill",
57 "BriefDescription": "L1D cache refill"
60 "PublicDescription": "Level 1 data cache access",
63 "BriefDescription": "L1D cache access"
66 "PublicDescription": "Level 1 data TLB refill",
72 "PublicDescription": "Level 1 instruction cache access",
75 "BriefDescription": "L1I cache access"
[all …]
|