| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/goldmont/ |
| D | frontend.json | 4 …Cache (ICache) for one or more bytes in an ICache Line and that cache line is in the ICache (hit).…
14 …Cache (ICache) for one or more bytes in an ICache Line and that cache line is not in the ICache (…
24 …Cache (ICache) for one or more bytes in an ICache Line. The event strives to count on a cache lin…
34 …MS) starts a flow of uops from the MSROM. It does not count every time a uop is read from the MSRO…
40 "BriefDescription": "MS decode starts"
44 …"PublicDescription": "Counts the number of times the prediction (from the predecode cache) for ins…
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/goldmontplus/ |
| D | frontend.json | 4 …Cache (ICache) for one or more bytes in an ICache Line and that cache line is in the ICache (hit).…
16 …Cache (ICache) for one or more bytes in an ICache Line and that cache line is not in the ICache (…
28 …Cache (ICache) for one or more bytes in an ICache Line. The event strives to count on a cache lin…
40 …MS) starts a flow of uops from the MSROM. It does not count every time a uop is read from the MSRO…
48 "BriefDescription": "MS decode starts"
52 …"PublicDescription": "Counts the number of times the prediction (from the predecode cache) for ins…
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/goldmont/ |
| D | frontend.json | 30 …"PublicDescription": "Counts the number of times the prediction (from the predecode cache) for ins…
38 …Cache (ICache) for one or more bytes in an ICache Line. The event strives to count on a cache lin…
46 …Cache (ICache) for one or more bytes in an ICache Line and that cache line is in the ICache (hit).…
54 …Cache (ICache) for one or more bytes in an ICache Line and that cache line is not in the ICache (…
59 "BriefDescription": "MS decode starts",
62 …MS) starts a flow of uops from the MSROM. It does not count every time a uop is read from the MSRO…
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/goldmontplus/ |
| D | frontend.json | 30 …"PublicDescription": "Counts the number of times the prediction (from the predecode cache) for ins…
38 …Cache (ICache) for one or more bytes in an ICache Line. The event strives to count on a cache lin…
46 …Cache (ICache) for one or more bytes in an ICache Line and that cache line is in the ICache (hit).…
54 …Cache (ICache) for one or more bytes in an ICache Line and that cache line is not in the ICache (…
59 "BriefDescription": "MS decode starts",
62 …MS) starts a flow of uops from the MSROM. It does not count every time a uop is read from the MSRO…
|
| /kernel/linux/linux-6.6/drivers/md/bcache/ |
| D | io.c | 1 // SPDX-License-Identifier: GPL-2.0
21 mempool_free(b, &c->bio_meta); in bch_bbio_free()
26 struct bbio *b = mempool_alloc(&c->bio_meta, GFP_NOIO); in bch_bbio_alloc()
27 struct bio *bio = &b->bio; in bch_bbio_alloc()
29 bio_init(bio, NULL, bio->bi_inline_vecs, in bch_bbio_alloc()
30 meta_bucket_pages(&c->cache->sb), 0); in bch_bbio_alloc()
39 bio->bi_iter.bi_sector = PTR_OFFSET(&b->key, 0); in __bch_submit_bbio()
40 bio_set_dev(bio, c->cache->bdev); in __bch_submit_bbio()
42 b->submit_time_us = local_clock_us(); in __bch_submit_bbio()
43 closure_bio_submit(c, bio, bio->bi_private); in __bch_submit_bbio()
[all …]
|
| /kernel/linux/linux-5.10/Documentation/admin-guide/device-mapper/ |
| D | writecache.rst | 6 doesn't cache reads because reads are supposed to be cached in page cache
14 1. type of the cache device - "p" or "s"
16 - p - persistent memory
17 - s - SSD
19 3. the cache device
26 offset from the start of cache device in 512-byte sectors
41 autocommit_time ms (default: 1000)
42 autocommit time in milliseconds. The data is automatically
43 commited if this time passes and no FLUSH request is
46 applicable only to persistent memory - use the FUA flag
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/power/supply/ |
| D | maxim,ds2760.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sebastian Reichel <sre@kernel.org>
13 The ds2760 is a w1 slave device and must hence have its sub-node in
17 - $ref: power-supply.yaml#
23 maxim,pmod-enabled:
29 maxim,cache-time-ms:
31 Time im milliseconds to cache the data for.
32 When this time expires, the values are read again from the hardware.
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/power/supply/ |
| D | maxim,ds2760.txt | 4 The ds2760 is a w1 slave device and must hence have its sub-node in DT
11 - compatible: must be "maxim,ds2760"
14 - power-supplies: Refers to one or more power supplies connected to
16 - maxim,pmod-enabled: This boolean property enables the DS2760 to enter
20 - maxim,cache-time-ms: Time im milliseconds to cache the data for. When
21 this time expires, the values are read again from
23 - rated-capacity-microamp-hours:
26 non-volatile chip memory is used.
|
| /kernel/linux/linux-6.6/Documentation/core-api/ |
| D | workqueue.rst | 33 thread system-wide. A single MT wq needed to keep around the same
50 limitation that no two polling PIOs can progress at the same time. As
60 * Use per-CPU unified worker pools shared by all wq to provide
83 called worker-pools.
85 The cmwq design differentiates between the user-facing workqueues that
87 which manages worker-pools and processes the queued work items.
89 There are two worker-pools, one for normal work items and the other
91 worker-pools to serve work items queued on unbound workqueues - the
102 When a work item is queued to a workqueue, the target worker-pool is
104 and appended on the shared worklist of the worker-pool. For example,
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/meteorlake/ |
| D | frontend.json | 15 …s the front-end is resteered when it finds a branch instruction in a fetch line. This is called Un…
24 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
38 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
41 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou…
73 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
85 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to …
112 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
118 …"PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.",
124 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
130 …"PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.",
[all …]
|
| /kernel/linux/linux-6.6/Documentation/admin-guide/device-mapper/ |
| D | writecache.rst | 6 doesn't cache reads because reads are supposed to be cached in page cache
14 1. type of the cache device - "p" or "s"
15 - p - persistent memory
16 - s - SSD
18 3. the cache device
25 offset from the start of cache device in 512-byte sectors
40 autocommit_time ms (default: 1000)
41 autocommit time in milliseconds. The data is automatically
42 committed if this time passes and no FLUSH request is
45 applicable only to persistent memory - use the FUA flag
[all …]
|
| /kernel/linux/linux-5.10/drivers/md/bcache/ |
| D | io.c | 1 // SPDX-License-Identifier: GPL-2.0
21 mempool_free(b, &c->bio_meta); in bch_bbio_free()
26 struct bbio *b = mempool_alloc(&c->bio_meta, GFP_NOIO); in bch_bbio_alloc()
27 struct bio *bio = &b->bio; in bch_bbio_alloc()
29 bio_init(bio, bio->bi_inline_vecs, meta_bucket_pages(&c->cache->sb)); in bch_bbio_alloc()
38 bio->bi_iter.bi_sector = PTR_OFFSET(&b->key, 0); in __bch_submit_bbio()
39 bio_set_dev(bio, PTR_CACHE(c, &b->key, 0)->bdev); in __bch_submit_bbio()
41 b->submit_time_us = local_clock_us(); in __bch_submit_bbio()
42 closure_bio_submit(c, bio, bio->bi_private); in __bch_submit_bbio()
50 bch_bkey_copy_single_ptr(&b->key, k, ptr); in bch_submit_bbio()
[all …]
|
| /kernel/linux/linux-5.10/sound/soc/codecs/ |
| D | ssm2518.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
142 static const DECLARE_TLV_DB_MINMAX_MUTE(ssm2518_vol_tlv, -7125, 2400);
143 static const DECLARE_TLV_DB_SCALE(ssm2518_compressor_tlv, -3400, 200, 0);
144 static const DECLARE_TLV_DB_SCALE(ssm2518_expander_tlv, -8100, 300, 0);
145 static const DECLARE_TLV_DB_SCALE(ssm2518_noise_gate_tlv, -9600, 300, 0);
146 static const DECLARE_TLV_DB_SCALE(ssm2518_post_drc_tlv, -2400, 300, 0);
149 0, 7, TLV_DB_SCALE_ITEM(-2200, 200, 0),
150 7, 15, TLV_DB_SCALE_ITEM(-800, 100, 0),
154 "0 ms", "0.1 ms", "0.19 ms", "0.37 ms", "0.75 ms", "1.5 ms", "3 ms",
[all …]
|
| /kernel/linux/linux-6.6/sound/soc/codecs/ |
| D | ssm2518.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
141 static const DECLARE_TLV_DB_MINMAX_MUTE(ssm2518_vol_tlv, -7125, 2400);
142 static const DECLARE_TLV_DB_SCALE(ssm2518_compressor_tlv, -3400, 200, 0);
143 static const DECLARE_TLV_DB_SCALE(ssm2518_expander_tlv, -8100, 300, 0);
144 static const DECLARE_TLV_DB_SCALE(ssm2518_noise_gate_tlv, -9600, 300, 0);
145 static const DECLARE_TLV_DB_SCALE(ssm2518_post_drc_tlv, -2400, 300, 0);
148 0, 7, TLV_DB_SCALE_ITEM(-2200, 200, 0),
149 7, 15, TLV_DB_SCALE_ITEM(-800, 100, 0),
153 "0 ms", "0.1 ms", "0.19 ms", "0.37 ms", "0.75 ms", "1.5 ms", "3 ms",
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/rocketlake/ |
| D | frontend.json | 6 … number of times the front-end is resteered when it finds a branch instruction in a fetch line. Th…
14 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
24 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
32 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou…
43 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
54 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to …
70 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
76 …"PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.",
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/tigerlake/ |
| D | frontend.json | 6 … number of times the front-end is resteered when it finds a branch instruction in a fetch line. Th…
14 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
24 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
32 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou…
43 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
54 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to …
70 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
76 …"PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.",
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/icelake/ |
| D | frontend.json | 6 … number of times the front-end is resteered when it finds a branch instruction in a fetch line. Th…
14 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
24 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
32 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou…
43 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
54 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to …
70 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
76 …"PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.",
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/Documentation/ |
| D | perf-trace.txt | 1 perf-trace(1)
5 ----
6 perf-trace - strace inspired tool
9 --------
15 -----------
22 but the session needs to include the raw_syscalls events (-e 'raw_syscalls:*').
30 -------
32 -a::
33 --all-cpus::
34 System-wide collection from all CPUs.
[all …]
|
| D | perf-stat.txt | 1 perf-stat(1)
5 ----
6 perf-stat - Run a command and gather performance counter statistics
9 --------
11 'perf stat' [-e <EVENT> | --event=EVENT] [-a] <command>
12 'perf stat' [-e <EVENT> | --event=EVENT] [-a] \-- <command> [<options>]
13 'perf stat' [-e <EVENT> | --event=EVENT] [-a] record [-o file] \-- <command> [<options>]
14 'perf stat' report [-i file]
17 -----------
23 -------
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/Documentation/ |
| D | perf-trace.txt | 1 perf-trace(1)
5 ----
6 perf-trace - strace inspired tool
9 --------
15 -----------
22 but the session needs to include the raw_syscalls events (-e 'raw_syscalls:*').
30 -------
32 -a::
33 --all-cpus::
34 System-wide collection from all CPUs.
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| D | frontend.json | 6 … number of times the front-end is resteered when it finds a branch instruction in a fetch line. Th…
14 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
22 …e Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Strea…
27 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
30 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th…
41 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
52 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to …
68 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
78 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/skylake/ |
| D | frontend.json | 6 … number of times the front-end is resteered when it finds a branch instruction in a fetch line. Th…
14 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
22 …e Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Strea…
27 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
30 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th…
41 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
52 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to …
68 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
78 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/skylakex/ |
| D | frontend.json | 6 … number of times the front-end is resteered when it finds a branch instruction in a fetch line. Th…
14 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
22 …e Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Strea…
27 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
30 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th…
41 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
52 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to …
68 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
78 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/icelakex/ |
| D | frontend.json | 6 … number of times the front-end is resteered when it finds a branch instruction in a fetch line. Th…
14 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
24 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
32 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou…
43 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
54 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to …
70 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
76 …"PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.",
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/alderlake/ |
| D | frontend.json | 15 …s the front-end is resteered when it finds a branch instruction in a fetch line. This is called Un…
24 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
38 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
41 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou…
53 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
65 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to …
83 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
89 …"PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.",
95 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
101 …"PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.",
[all …]
|