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/device/soc/rockchip/common/kernel/drivers/gpu/arm/mali400/mali/common/
Dmali_l2_cache.c19 * Size of the Mali L2 cache registers in bytes
24 * Mali L2 cache register numbers
43 * Mali L2 cache commands
44 * These are the commands that can be sent to the Mali L2 cache unit
51 * Mali L2 cache commands
52 * These are the commands that can be sent to the Mali L2 cache unit
61 * Mali L2 cache status bits
79 static void mali_l2_cache_reset(struct mali_l2_cache_core *cache);
82 struct mali_l2_cache_core *cache, u32 reg, u32 val);
84 static void mali_l2_cache_lock(struct mali_l2_cache_core *cache) in mali_l2_cache_lock() argument
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Dmali_l2_cache.h18 /* Maximum 1 GP and 4 PP for an L2 cache core (Mali-400 MP4) */
22 * Definition of the L2 cache core struct
23 * Used to track a L2 cache unit in the system.
30 /* Synchronize L2 cache access */
36 /* The power domain this L2 cache belongs to */
39 /* MALI_TRUE if power is on for this L2 cache */
72 void mali_l2_cache_delete(struct mali_l2_cache_core *cache);
74 MALI_STATIC_INLINE u32 mali_l2_cache_get_id(struct mali_l2_cache_core *cache) in mali_l2_cache_get_id() argument
76 MALI_DEBUG_ASSERT_POINTER(cache); in mali_l2_cache_get_id()
77 return cache->core_id; in mali_l2_cache_get_id()
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/device/soc/rockchip/common/vendor/drivers/gpu/arm/mali400/mali/common/
Dmali_l2_cache.c20 * Size of the Mali L2 cache registers in bytes
25 * Mali L2 cache register numbers
44 * Mali L2 cache commands
45 * These are the commands that can be sent to the Mali L2 cache unit
52 * Mali L2 cache commands
53 * These are the commands that can be sent to the Mali L2 cache unit
62 * Mali L2 cache status bits
80 static void mali_l2_cache_reset(struct mali_l2_cache_core *cache);
82 static mali_osk_errcode_t mali_l2_cache_send_command(struct mali_l2_cache_core *cache, u32 reg, u32…
84 static void mali_l2_cache_lock(struct mali_l2_cache_core *cache) in mali_l2_cache_lock() argument
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Dmali_l2_cache.h19 /* Maximum 1 GP and 4 PP for an L2 cache core (Mali-400 MP4) */
23 * Definition of the L2 cache core struct
24 * Used to track a L2 cache unit in the system.
31 /* Synchronize L2 cache access */
37 /* The power domain this L2 cache belongs to */
40 /* MALI_TRUE if power is on for this L2 cache */
72 void mali_l2_cache_delete(struct mali_l2_cache_core *cache);
74 MALI_STATIC_INLINE u32 mali_l2_cache_get_id(struct mali_l2_cache_core *cache) in mali_l2_cache_get_id() argument
76 MALI_DEBUG_ASSERT_POINTER(cache); in mali_l2_cache_get_id()
77 return cache->core_id; in mali_l2_cache_get_id()
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/device/soc/hisilicon/ws63v100/sdk/open_source/libcoap/libcoap/include/coap3/
Dcoap_cache.h13 * @brief Provides a simple cache request storage for CoAP requests
23 * @defgroup cache Cache Support
24 * API for Cache-Key and Cache-Entry.
30 * Callback to free off the app data when the cache-entry is
48 * Calculates a cache-key for the given CoAP PDU. See
50 * for an explanation of CoAP cache keys.
52 * Specific CoAP options can be removed from the cache-key. Examples of
59 * NOTE: The returned cache-key needs to be freed off by the caller by
62 * @param session The session to add into cache-key if @p session_based
64 * @param pdu The CoAP PDU for which a cache-key is to be
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Dcoap_cache_internal.h2 * coap_cache_internal.h -- Cache functions for libcoap
14 * @brief CoAP cache internal information
27 * @defgroup cache_internal Cache Support
28 * Internal API for Cache-Key and Cache-Entry support
/device/soc/hisilicon/hi3861v100/sdk_liteos/third_party/mbedtls/include/mbedtls/
Dssl_cache.h4 * \brief SSL session cache implementation
52 #define MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES 50 /*!< Maximum entries in cache */
65 * \brief This structure is used for storing cache entries
80 * \brief Cache context
85 int timeout; /*!< cache entry timeout */
93 * \brief Initialize an SSL cache context
95 * \param cache SSL cache context
97 void mbedtls_ssl_cache_init( mbedtls_ssl_cache_context *cache );
100 * \brief Cache get callback implementation
103 * \param data SSL cache context
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/device/soc/hisilicon/ws63v100/sdk/open_source/mbedtls/mbedtls_v3.1.0/library/
Dssl_cache.c2 * SSL session cache implementation
41 void mbedtls_ssl_cache_init( mbedtls_ssl_cache_context *cache ) in mbedtls_ssl_cache_init() argument
43 memset( cache, 0, sizeof( mbedtls_ssl_cache_context ) ); in mbedtls_ssl_cache_init()
45 cache->timeout = MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT; in mbedtls_ssl_cache_init()
46 cache->max_entries = MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES; in mbedtls_ssl_cache_init()
49 mbedtls_mutex_init( &cache->mutex ); in mbedtls_ssl_cache_init()
53 static int ssl_cache_find_entry( mbedtls_ssl_cache_context *cache, in ssl_cache_find_entry() argument
64 for( cur = cache->chain; cur != NULL; cur = cur->next ) in ssl_cache_find_entry()
67 if( cache->timeout != 0 && in ssl_cache_find_entry()
68 (int) ( t - cur->timestamp ) > cache->timeout ) in ssl_cache_find_entry()
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/device/soc/hisilicon/ws63v100/sdk/open_source/mbedtls/mbedtls_v3.1.0/include/mbedtls/
Dssl_cache.h4 * \brief SSL session cache implementation
47 #define MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES 50 /*!< Maximum entries in cache */
60 * \brief This structure is used for storing cache entries
78 * \brief Cache context
83 int MBEDTLS_PRIVATE(timeout); /*!< cache entry timeout */
91 * \brief Initialize an SSL cache context
93 * \param cache SSL cache context
95 void mbedtls_ssl_cache_init( mbedtls_ssl_cache_context *cache );
98 * \brief Cache get callback implementation
101 * \param data The SSL cache context to use.
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/device/soc/hisilicon/ws63v100/sdk/kernel/liteos/liteos_v208.5.0/Huawei_LiteOS/open_source/CMSIS/CMSIS/Core/Include/
Dcachel1_armv7.h3 * @brief CMSIS Level 1 Cache API for Armv7-M and later
36 \defgroup CMSIS_Core_CacheFunctions Cache Functions
37 \brief Functions that configure Instruction and Data cache.
41 /* Cache Size ID Register Macros */
46 #define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). …
50 #define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). …
54 \brief Enable I-Cache
55 \details Turns on I-Cache
64 SCB->ICIALLU = 0UL; /* invalidate I-Cache */ in SCB_EnableICache()
67 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
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Dpmu_armv8.h40 #define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */
41 #define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */
42 #define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */
56 …MU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */
57 #define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache wri…
58 #define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache acc…
59 #define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache ref…
60 #define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache wri…
66 #define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache all…
67 #define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache all…
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/device/soc/hisilicon/ws63v100/sdk/kernel/liteos/liteos_v208.5.0/Huawei_LiteOS/arch/riscv/include/arch/
Dcache.h3 * Description : Cache operations HeadFile
30 * @defgroup cache
63 /* riscv cache register config */
65 …* csr_bit[0] ICEN Instruction cache is enabled when this bit is set to 1b1. Default is disable…
66 …* Bit[2:1] ICS Instruction cache size: 2b00=4KB, 2b01=8KB, 2b10=16KB, 2b11=32KB. Default is…
72 * Bit[0] DCEN Data cache is enabled when this bit is set to 1b1. Default is disabled.
73 * Bit[2:1] DCS Data cache size: 2b00=4KB, 2b01=8KB, 2b10=16KB, 2b11=32KB. Default is 32KB
79 * Bit[0] VA Instruction cache invalidation by all or VA: 1b0=all, 1b1=VA.
80 * Bit[2] ICIV Initiate instruction cache invalidation when this bit is set to 1b1.
81 … When the instruction cache invalidation is by VA, the virtual address is specified in icinva CSR
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/device/soc/hisilicon/ws63v100/sdk/build/cmake/
Dglobal_variable.cmake6 set(ALL_PUBLIC_HEADER "" CACHE INTERNAL "" FORCE)
7 set(ALL_HEADER "" CACHE INTERNAL "" FORCE)
8 set(ALL_PUBLIC_DEFINES ${DEFINES} CACHE INTERNAL "" FORCE)
9 set(ALL_PUBLIC_CCFLAGS "${CCFLAGS}" CACHE INTERNAL "" FORCE)
10 set(ALL_SOURCES "" CACHE INTERNAL "" FORCE)
11 set(LOS_LIB "" CACHE INTERNAL "" FORCE)
12 set(LINKER_DIR "" CACHE INTERNAL "" FORCE)
13 set(SDK_PROJECT_FILE_DIR "" CACHE INTERNAL "" FORCE)
14 set(LOG_DEF_LIST "" CACHE INTERNAL "" FORCE)
15 set(WSTP_HEADER_LIST "" CACHE INTERNAL "" FORCE)
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Dbuild_component.cmake17 set(${COMPONENT_NAME}_MODULE_NAME ${MODULE_NAME} CACHE INTERNAL "" FORCE)
18 set(${COMPONENT_NAME}_AUTO_DEF ${AUTO_DEF_FILE_ID} CACHE INTERNAL "" FORCE)
19 set(${COMPONENT_NAME}_SOURCES ${SOURCES} CACHE INTERNAL "" FORCE)
140 set(SDK_PROJECT_FILE_DIR "${CMAKE_CURRENT_SOURCE_DIR}" CACHE INTERNAL "" FORCE)
141 set(MAIN_COMPONENT "${COMPONENT_NAME}" CACHE INTERNAL "" FORCE)
147 set(LOG_DEF_LIST "${LOG_DEF_LIST}" "${LOG_DEF}" CACHE INTERNAL "" FORCE)
288 set(ALL_PUBLIC_HEADER "${ALL_PUBLIC_HEADER}" "${PUBLIC_HEADER}" CACHE INTERNAL "" FORCE)
294 … set(ALL_HEADER_DIRS "${ALL_HEADER_DIRS}" "${PUBLIC_HEADER}" CACHE INTERNAL "" FORCE)
299 … set(ALL_HEADER_DIRS "${ALL_HEADER_DIRS}" "${PRIVATE_HEADER}" CACHE INTERNAL "" FORCE)
304 set(ALL_DEFINES "${ALL_DEFINES}" "${PUBLIC_DEFINES}" CACHE INTERNAL "" FORCE)
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/device/qemu/SmartL_E802/liteos_m/board/hals/csky_driver/include/
Dcore_802.h135 - Core Cache Register
196 \brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
439 \brief Type definitions for the cache Registers
444 \brief On chip cache structure.
448 __IOM uint32_t CER; /*!< Offset: 0x000 (R/W) Cache enable register */
449 __IOM uint32_t CIR; /*!< Offset: 0x004 (R/W) Cache invalid register */
450 __IOM uint32_t CRCR[4U]; /*!< Offset: 0x008 (R/W) Cache Configuration register */
452 …__IOM uint32_t CPFCR; /*!< Offset: 0xFF4 (R/W) Cache performance analysis contro…
453 __IOM uint32_t CPFATR; /*!< Offset: 0xFF8 (R/W) Cache access times register */
454 __IOM uint32_t CPFMTR; /*!< Offset: 0xFFC (R/W) Cache missing times register */
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/device/soc/hisilicon/ws63v100/sdk/middleware/utils/dfx/log_file/
Dlog_file.c73 store_cache_t *cache = file_info->cache; in logfile_write_to_cache() local
76 tmp_pos = (int32_t)cache->cache_read_pos; in logfile_write_to_cache()
77 uint32_t record_len_written = cache->cache_size - cache->cache_write_pos; in logfile_write_to_cache()
80 … if (memcpy_s(&(cache->data[cache->cache_write_pos]), record_len_written, data, data_len) != EOK) { in logfile_write_to_cache()
83 cache->cache_write_pos += data_len; in logfile_write_to_cache()
87 …memcpy_s(&(cache->data[cache->cache_write_pos]), record_len_written, data, record_len_written) != … in logfile_write_to_cache()
90 cache->cache_write_pos = 0; in logfile_write_to_cache()
93 … memcpy_s(&(cache->data[cache->cache_write_pos]), (uint32_t)tmp_pos, data + record_len_written, in logfile_write_to_cache()
97 cache->cache_write_pos += record_len_remained; in logfile_write_to_cache()
137 if (g_logfile_manage.file_info[i].cache != NULL) { in logfile_timer_handler()
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Dlog_file_flash.c124 store_cache_t *cache = file_info->cache; in logfile_write_cache_to_flash() local
130 tmp_pos = cache->cache_write_pos; in logfile_write_cache_to_flash()
133 if (tmp_pos == cache->cache_read_pos) { in logfile_write_cache_to_flash()
137 read_data = (uint8_t *)cache->data + cache->cache_read_pos; in logfile_write_cache_to_flash()
140 if (tmp_pos > cache->cache_read_pos) { in logfile_write_cache_to_flash()
141 read_len = (int32_t)(tmp_pos - cache->cache_read_pos); in logfile_write_cache_to_flash()
144 read_len = (int32_t)(cache->cache_size - cache->cache_read_pos); in logfile_write_cache_to_flash()
146 write_cache_to_flash(file_info, (uint8_t *)cache->data, tmp_pos); in logfile_write_cache_to_flash()
149 cache->cache_read_pos = tmp_pos; in logfile_write_cache_to_flash()
/device/soc/hisilicon/ws63v100/sdk/open_source/wpa_supplicant/src/rsn_supp/
Dpmksa_cache.c2 * WPA Supplicant - RSN PMKSA cache
23 struct rsn_pmksa_cache_entry *pmksa; /* PMKSA cache */
24 int pmksa_count; /* number of entries in PMKSA cache */
75 "RSN: postpone PMKSA cache entry expiration for SAE with " in pmksa_cache_expire()
82 wpa_printf(MSG_DEBUG, "RSN: expired PMKSA cache entry for " in pmksa_cache_expire()
153 * pmksa_cache_add - Add a PMKSA cache entry
154 * @pmksa: Pointer to PMKSA cache data from pmksa_cache_init()
164 * @cache_id: Pointer to FILS Cache Identifier or %NULL if not advertised
165 * Returns: Pointer to the added PMKSA cache entry or %NULL on error
168 * cache. If an old entry is already in the cache for the same Authenticator,
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/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/backend/gpu/
Dmali_kbase_pm_l2_states.h23 * Backend-specific Power Manager level 2 cache state definitions.
28 * @OFF: The L2 cache and tiler are off
29 * @PEND_ON: The L2 cache and tiler are powering on
31 * @ON_HWCNT_ENABLE: The L2 cache and tiler are on, and hwcnt is being enabled
32 * @ON: The L2 cache and tiler are on, and hwcnt is enabled
33 * @ON_HWCNT_DISABLE: The L2 cache and tiler are on, and hwcnt is being disabled
36 * @POWER_DOWN: The L2 cache and tiler are about to be powered off
37 * @PEND_OFF: The L2 cache and tiler are powering off
38 * @RESET_WAIT: The GPU is resetting, L2 cache and tiler power state are
/device/soc/hisilicon/ws63v100/sdk/open_source/wpa_supplicant/src/ap/
Dpmksa_cache_auth.c2 * hostapd - PMKSA cache for IEEE 802.11i RSN
105 * pmksa_cache_auth_flush - Flush all PMKSA cache entries
106 * @pmksa: Pointer to PMKSA cache data from pmksa_cache_auth_init()
111 wpa_warning_log4(MSG_DEBUG, "RSN: Flush PMKSA cache entry for " in pmksa_cache_auth_flush()
127 wpa_warning_log4(MSG_DEBUG, "RSN: expired PMKSA cache entry for " in pmksa_cache_expire()
271 wpa_warning_log4(MSG_DEBUG, "RSN: added PMKSA cache entry for " "%02x:xx:xx:%02x:%02x:%02x", in pmksa_cache_link_entry()
278 * pmksa_cache_auth_add - Add a PMKSA cache entry
279 * @pmksa: Pointer to PMKSA cache data from pmksa_cache_auth_init()
290 * Returns: Pointer to the added PMKSA cache entry or %NULL on error
293 * cache. If an old entry is already in the cache for the same Supplicant,
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/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/device/
Dmali_kbase_device.h121 * kbase_gpu_cache_flush_and_busy_wait - Start a cache flush and busy wait
125 * Issue a cache flush command to hardware, then busy wait an irq status.
128 * after the busy-wait is done. Any pended cache flush commands raised by
138 * kbase_gpu_start_cache_clean - Start a cache clean
142 * Issue a given cache flush command to hardware.
148 * kbase_gpu_start_cache_clean_nolock - Start a cache clean
152 * Issue a given cache flush command to hardware.
159 * kbase_gpu_wait_cache_clean - Wait for cache cleaning to finish
167 * kbase_gpu_wait_cache_clean_timeout - Wait for certain time for cache
170 * @wait_timeout_ms: Time in milliseconds, to wait for cache clean to complete.
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/device/soc/hisilicon/hi3861v100/sdk_liteos/third_party/u-boot-v2019.07/patch/
DCVE-2019-13105.patch6 ext_cache_read doesn't null cache->buf, after freeing, which results
19 @@ -286,7 +286,7 @@ int ext_cache_read(struct ext_block_cache *cache, lbaint_t block, int size)
20 if (!cache->buf)
22 if (!ext4fs_devread(block, 0, size, cache->buf)) {
23 - free(cache->buf);
24 + ext_cache_fini(cache);
27 cache->block = block;
/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/device/
Dmali_kbase_device.h111 * kbase_gpu_start_cache_clean - Start a cache clean
114 * Issue a cache clean and invalidate command to hardware. This function will
120 * kbase_gpu_start_cache_clean_nolock - Start a cache clean
123 * Issue a cache clean and invalidate command to hardware. hwaccess_lock
129 * kbase_gpu_wait_cache_clean - Wait for cache cleaning to finish
137 * kbase_gpu_wait_cache_clean_timeout - Wait for certain time for cache
140 * @wait_timeout_ms: Time in milliseconds, to wait for cache clean to complete.
144 * completion of cache clean operation can cause deadlock, as the operation may
152 * kbase_gpu_cache_clean_wait_complete - Called after the cache cleaning is
162 * kbase_clean_caches_done - Issue preiously queued cache clean request or
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/device/soc/hisilicon/ws63v100/sdk/protocol/bt/host/bt/
Dbt_host.cmake7 set(BTH_RAM_LIST "" CACHE INTERNAL "" FORCE)
8 set(BTA_RAM_LIST "" CACHE INTERNAL "" FORCE)
10 set(BTH_PUBLIC_HDR_LIST "" CACHE INTERNAL "" FORCE)
11 set(BTH_PRIVATE_HDR_LIST "" CACHE INTERNAL "" FORCE)
13 set(BTH_ROM_LIST "" CACHE INTERNAL "" FORCE)
14 set(BTA_ROM_LIST "" CACHE INTERNAL "" FORCE)
/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/gpu/
Dmali_kbase_gpu_regmap.h38 #define L2_FEATURES 0x004 /* (RO) Level 2 cache features */
57 #define L2_CONFIG 0x048 /* (RW) Level 2 cache configuration */
93 #define L2_PRESENT_LO 0x120 /* (RO) Level 2 cache present bitmap, low word */
94 #define L2_PRESENT_HI 0x124 /* (RO) Level 2 cache present bitmap, high word */
105 #define L2_READY_LO 0x160 /* (RO) Level 2 cache ready bitmap, low word */
106 #define L2_READY_HI 0x164 /* (RO) Level 2 cache ready bitmap, high word */
117 #define L2_PWRON_LO 0x1A0 /* (WO) Level 2 cache power on bitmap, low word */
118 #define L2_PWRON_HI 0x1A4 /* (WO) Level 2 cache power on bitmap, high word */
129 #define L2_PWROFF_LO 0x1E0 /* (WO) Level 2 cache power off bitmap, low word */
130 #define L2_PWROFF_HI 0x1E4 /* (WO) Level 2 cache power off bitmap, high word */
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