Searched full:cacheability (Results 1 – 25 of 52) sorted by relevance
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| /kernel/linux/linux-6.6/arch/x86/include/asm/ |
| D | agp.h | 12 * mappings with different cacheability attributes for the same
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| D | set_memory.h | 15 * Cacheability : UnCached, WriteCombining, WriteThrough, WriteBack
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/ |
| D | arm,gic-v3.yaml | 112 and cacheability attributes but are connected to a non-coherent
205 cacheability attributes but is connected to a non-coherent
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| /kernel/linux/linux-5.10/arch/xtensa/mm/ |
| D | highmem.c | 67 * is a bad idea also, in case the page changes cacheability in kunmap_atomic_high()
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| /kernel/linux/linux-5.10/arch/x86/mm/ |
| D | highmem_32.c | 50 * is a bad idea also, in case the page changes cacheability in kunmap_atomic_high()
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| D | iomap_32.c | 106 * is a bad idea also, in case the page changes cacheability in iounmap_atomic()
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| /kernel/linux/linux-5.10/arch/c6x/include/asm/ |
| D | cache.h | 49 * This is the granularity of hardware cacheability control.
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| /kernel/linux/linux-5.10/drivers/iommu/ |
| D | msm_iommu.h | 16 /* Cacheability attributes of MSM IOMMU mappings */
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| /kernel/linux/linux-6.6/drivers/iommu/ |
| D | msm_iommu.h | 16 /* Cacheability attributes of MSM IOMMU mappings */
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| /kernel/linux/linux-5.10/arch/c6x/kernel/ |
| D | setup.c | 312 /* align to cacheability granularity */ in setup_arch()
318 /* align to cacheability granularity */ in setup_arch()
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| /kernel/linux/linux-6.6/arch/sparc/include/asm/ |
| D | swift.h | 21 #define SWIFT_AC 0x00008000 /* Alternate Cacheability (see viking.h) */
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| /kernel/linux/linux-5.10/arch/sparc/include/asm/ |
| D | swift.h | 21 #define SWIFT_AC 0x00008000 /* Alternate Cacheability (see viking.h) */
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| /kernel/linux/linux-6.6/arch/powerpc/kernel/ |
| D | cpu_setup_ppc970.S | 41 li r3,0x1200 /* enable i-fetch cacheability */
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| /kernel/linux/linux-5.10/arch/powerpc/kernel/ |
| D | cpu_setup_ppc970.S | 41 li r3,0x1200 /* enable i-fetch cacheability */
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| /kernel/linux/linux-5.10/arch/nds32/kernel/ |
| D | head.S | 70 /* set NTC cacheability, mutliple page size in use */
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| /kernel/linux/linux-6.6/include/linux/ |
| D | io-pgtable.h | 86 * IO_PGTABLE_QUIRK_ARM_OUTER_WBWA: Override the outer-cacheability
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| /kernel/linux/linux-5.10/arch/c6x/platforms/ |
| D | cache.c | 320 * Cacheability controls
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/ |
| D | intel_gtt.c | 346 * The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
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| D | intel_mocs.c | 138 * Thus it is expected to allow LLC cacheability to enable coherent
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| D | intel_gtt.h | 89 * Cacheability Control is a 4-bit value. The low three bits are stored in bits
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| /kernel/linux/linux-5.10/arch/powerpc/include/asm/ |
| D | reg_booke.h | 180 #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
181 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
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| /kernel/linux/linux-6.6/arch/powerpc/include/asm/ |
| D | reg_booke.h | 180 #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
181 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
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| /kernel/linux/linux-6.6/arch/arm/include/asm/ |
| D | io.h | 340 * Function Memory type Cacheability Cache hint
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| /kernel/linux/linux-5.10/arch/arm/include/asm/ |
| D | io.h | 357 * Function Memory type Cacheability Cache hint
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| /kernel/linux/linux-5.10/drivers/iommu/arm/arm-smmu-v3/ |
| D | arm-smmu-v3.h | 88 /* CR1 cacheability fields don't quite follow the usual TCR-style encoding */
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