| /kernel/linux/linux-5.10/drivers/i2c/busses/ |
| D | i2c-qcom-cci.c | 108 struct cci;
116 struct cci *cci; member
127 struct cci { struct
139 struct cci *cci = dev; in cci_isr() argument
143 val = readl(cci->base + CCI_IRQ_STATUS_0); in cci_isr()
144 writel(val, cci->base + CCI_IRQ_CLEAR_0); in cci_isr()
145 writel(0x1, cci->base + CCI_IRQ_GLOBAL_CLEAR_CMD); in cci_isr()
148 complete(&cci->master[0].irq_complete); in cci_isr()
149 if (cci->master[1].master) in cci_isr()
150 complete(&cci->master[1].irq_complete); in cci_isr()
[all …]
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| /kernel/linux/linux-6.6/drivers/i2c/busses/ |
| D | i2c-qcom-cci.c | 108 struct cci;
116 struct cci *cci; member
127 struct cci { struct
139 struct cci *cci = dev; in cci_isr() argument
143 val = readl(cci->base + CCI_IRQ_STATUS_0); in cci_isr()
144 writel(val, cci->base + CCI_IRQ_CLEAR_0); in cci_isr()
145 writel(0x1, cci->base + CCI_IRQ_GLOBAL_CLEAR_CMD); in cci_isr()
148 complete(&cci->master[0].irq_complete); in cci_isr()
149 if (cci->master[1].master) in cci_isr()
150 complete(&cci->master[1].irq_complete); in cci_isr()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/ |
| D | cci.txt | 2 ARM CCI cache coherent interconnect binding description
6 cache coherent interconnect (CCI) that is capable of monitoring bus
14 * CCI interconnect node
16 Description: Describes a CCI cache coherent Interconnect component
18 Node name must be "cci".
20 through the CCI interconnect is the same as the one seen from the
22 Every CCI node has to define the following properties:
28 "arm,cci-400"
29 "arm,cci-500"
30 "arm,cci-550"
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/ |
| D | arm,cci-400.yaml | 4 $id: http://devicetree.org/schemas/arm/arm,cci-400.yaml#
7 title: ARM CCI Cache Coherent Interconnect
14 coherent interconnect (CCI) that is capable of monitoring bus transactions
24 pattern: "^cci(@[0-9a-f]+)?$"
28 - arm,cci-400
29 - arm,cci-500
30 - arm,cci-550
35 Specifies base physical address of CCI control registers common to all
48 const: arm,cci-400-ctrl-if
71 - const: arm,cci-400-pmu,r0
[all …]
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| D | cci-control-port.yaml | 4 $id: http://devicetree.org/schemas/arm/cci-control-port.yaml#
7 title: CCI Interconnect Bus Masters
13 Masters in the device tree connected to a CCI port (inclusive of CPUs
19 cci-control-port:
33 cci-control-port = <&cci_control1>;
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/i2c/ |
| D | qcom,i2c-cci.yaml | 4 $id: http://devicetree.org/schemas/i2c/qcom,i2c-cci.yaml#
7 title: Qualcomm Camera Control Interface (CCI) I2C controller
17 - qcom,msm8226-cci
18 - qcom,msm8974-cci
19 - qcom,msm8996-cci
23 - qcom,msm8916-cci
24 - const: qcom,msm8226-cci # CCI v1
28 - qcom,sdm845-cci
29 - qcom,sm6350-cci
30 - qcom,sm8250-cci
[all …]
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| /kernel/linux/linux-5.10/drivers/bus/ |
| D | arm-cci.c | 2 * CCI cache coherent interconnect driver
17 #include <linux/arm-cci.h>
49 {.compatible = "arm,cci-400", .data = CCI400_PORTS_DATA },
52 { .compatible = "arm,cci-500", },
53 { .compatible = "arm,cci-550", },
59 OF_DEV_AUXDATA("arm,cci-400-pmu", 0, NULL, &cci_ctrl_base),
60 OF_DEV_AUXDATA("arm,cci-400-pmu,r0", 0, NULL, &cci_ctrl_base),
61 OF_DEV_AUXDATA("arm,cci-400-pmu,r1", 0, NULL, &cci_ctrl_base),
62 OF_DEV_AUXDATA("arm,cci-500-pmu,r0", 0, NULL, &cci_ctrl_base),
63 OF_DEV_AUXDATA("arm,cci-550-pmu,r0", 0, NULL, &cci_ctrl_base),
[all …]
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| /kernel/linux/linux-6.6/drivers/bus/ |
| D | arm-cci.c | 2 * CCI cache coherent interconnect driver
17 #include <linux/arm-cci.h>
49 {.compatible = "arm,cci-400", .data = CCI400_PORTS_DATA },
52 { .compatible = "arm,cci-500", },
53 { .compatible = "arm,cci-550", },
59 OF_DEV_AUXDATA("arm,cci-400-pmu", 0, NULL, &cci_ctrl_base),
60 OF_DEV_AUXDATA("arm,cci-400-pmu,r0", 0, NULL, &cci_ctrl_base),
61 OF_DEV_AUXDATA("arm,cci-400-pmu,r1", 0, NULL, &cci_ctrl_base),
62 OF_DEV_AUXDATA("arm,cci-500-pmu,r0", 0, NULL, &cci_ctrl_base),
63 OF_DEV_AUXDATA("arm,cci-550-pmu,r0", 0, NULL, &cci_ctrl_base),
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/i2c/ |
| D | i2c-qcom-cci.txt | 1 Qualcomm Camera Control Interface (CCI) I2C controller
9 "qcom,msm8916-cci"
10 "qcom,msm8996-cci"
11 "qcom,sdm845-cci"
16 Definition: base address CCI I2C controller and length of memory
22 Definition: specifies the CCI I2C interrupt. The format of the
35 Definition: a list of clock names, must include "cci" clock.
38 Usage: required for "qcom,msm8996-cci"
44 The CCI provides I2C masters for one (msm8916) or two i2c busses (msm8996 and
52 Definition: Index of the CCI bus/master
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/interconnect/ |
| D | mediatek,cci.yaml | 4 $id: http://devicetree.org/schemas/interconnect/mediatek,cci.yaml#
7 title: MediaTek Cache Coherent Interconnect (CCI) frequency and voltage scaling
14 MediaTek Cache Coherent Interconnect (CCI) is a hardware engine used by
21 - mediatek,mt8183-cci
22 - mediatek,mt8186-cci
35 - const: cci
44 Phandle of the regulator for CCI that provides the supply voltage.
48 Phandle of the regulator for sram of CCI that provides the supply
66 cci: cci {
67 compatible = "mediatek,mt8183-cci";
[all …]
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| /kernel/linux/linux-5.10/drivers/perf/ |
| D | Kconfig | 10 tristate "ARM CCI PMU driver"
14 Support for PMU events monitoring on the ARM CCI (Cache Coherent
17 If compiled as a module, it will be called arm-cci.
20 bool "support CCI-400"
25 CCI-400 provides 4 independent event counters counting events related
29 bool "support CCI-500/CCI-550"
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
35 internal events to the CCI.
|
| D | arm-cci.c | 2 // CCI Cache Coherent Interconnect PMU driver
6 #include <linux/arm-cci.h>
19 #define DRIVER_NAME "ARM-CCI PMU"
165 * Instead of an event id to monitor CCI cycles, a dedicated counter is
166 * provided. Use 0xff to represent CCI cycles and hope that no future revisions
177 * CCI PMU event id is an 8-bit value made of two parts - bits 7:5 for one of 8
638 * Program the CCI PMU counters which have PERF_HES_ARCH set
752 * For all counters on the CCI-PMU, disable any 'enabled' counters,
791 * by the cci
837 dev_err(&pmu_device->dev, "no irqs for CCI PMUs defined\n"); in pmu_request_irq()
[all …]
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| /kernel/linux/linux-5.10/drivers/usb/typec/ucsi/ |
| D | trace.c | 36 const char *ucsi_cci_str(u32 cci) in ucsi_cci_str() argument
38 if (UCSI_CCI_CONNECTOR(cci)) { in ucsi_cci_str()
39 if (cci & UCSI_CCI_ACK_COMPLETE) in ucsi_cci_str()
41 if (cci & UCSI_CCI_COMMAND_COMPLETE) in ucsi_cci_str()
45 if (cci & UCSI_CCI_ACK_COMPLETE) in ucsi_cci_str()
47 if (cci & UCSI_CCI_COMMAND_COMPLETE) in ucsi_cci_str()
|
| D | ucsi_acpi.c | 106 u32 cci; in ucsi_acpi_notify() local
109 ret = ucsi_acpi_read(ua->ucsi, UCSI_CCI, &cci, sizeof(cci)); in ucsi_acpi_notify()
113 if (UCSI_CCI_CONNECTOR(cci)) in ucsi_acpi_notify()
114 ucsi_connector_change(ua->ucsi, UCSI_CCI_CONNECTOR(cci)); in ucsi_acpi_notify()
116 if (cci & UCSI_CCI_ACK_COMPLETE && test_bit(ACK_PENDING, &ua->flags)) in ucsi_acpi_notify()
118 if (cci & UCSI_CCI_COMMAND_COMPLETE && in ucsi_acpi_notify()
|
| /kernel/linux/linux-6.6/drivers/usb/typec/ucsi/ |
| D | trace.c | 36 const char *ucsi_cci_str(u32 cci) in ucsi_cci_str() argument
38 if (UCSI_CCI_CONNECTOR(cci)) { in ucsi_cci_str()
39 if (cci & UCSI_CCI_ACK_COMPLETE) in ucsi_cci_str()
41 if (cci & UCSI_CCI_COMMAND_COMPLETE) in ucsi_cci_str()
45 if (cci & UCSI_CCI_ACK_COMPLETE) in ucsi_cci_str()
47 if (cci & UCSI_CCI_COMMAND_COMPLETE) in ucsi_cci_str()
|
| /kernel/linux/linux-6.6/drivers/perf/ |
| D | Kconfig | 10 tristate "ARM CCI PMU driver"
14 Support for PMU events monitoring on the ARM CCI (Cache Coherent
17 If compiled as a module, it will be called arm-cci.
20 bool "support CCI-400"
25 CCI-400 provides 4 independent event counters counting events related
29 bool "support CCI-500/CCI-550"
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
35 internal events to the CCI.
|
| D | arm-cci.c | 2 // CCI Cache Coherent Interconnect PMU driver
6 #include <linux/arm-cci.h>
16 #define DRIVER_NAME "ARM-CCI PMU"
162 * Instead of an event id to monitor CCI cycles, a dedicated counter is
163 * provided. Use 0xff to represent CCI cycles and hope that no future revisions
174 * CCI PMU event id is an 8-bit value made of two parts - bits 7:5 for one of 8
635 * Program the CCI PMU counters which have PERF_HES_ARCH set
749 * For all counters on the CCI-PMU, disable any 'enabled' counters,
788 * by the cci
834 dev_err(&pmu_device->dev, "no irqs for CCI PMUs defined\n"); in pmu_request_irq()
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | exynos5420-cpus.dtsi | 31 cci-control-port = <&cci_control1>;
43 cci-control-port = <&cci_control1>;
55 cci-control-port = <&cci_control1>;
67 cci-control-port = <&cci_control1>;
79 cci-control-port = <&cci_control0>;
91 cci-control-port = <&cci_control0>;
103 cci-control-port = <&cci_control0>;
115 cci-control-port = <&cci_control0>;
|
| D | exynos5422-cpus.dtsi | 30 cci-control-port = <&cci_control0>;
43 cci-control-port = <&cci_control0>;
56 cci-control-port = <&cci_control0>;
69 cci-control-port = <&cci_control0>;
82 cci-control-port = <&cci_control1>;
95 cci-control-port = <&cci_control1>;
108 cci-control-port = <&cci_control1>;
121 cci-control-port = <&cci_control1>;
|
| D | exynos5260.dtsi | 41 cci-control-port = <&cci_control1>;
48 cci-control-port = <&cci_control1>;
55 cci-control-port = <&cci_control0>;
62 cci-control-port = <&cci_control0>;
69 cci-control-port = <&cci_control0>;
76 cci-control-port = <&cci_control0>;
200 cci: cci@10f00000 { label
201 compatible = "arm,cci-400";
208 compatible = "arm,cci-400-ctrl-if";
214 compatible = "arm,cci-400-ctrl-if";
|
| /kernel/linux/linux-5.10/arch/ia64/kernel/ |
| D | topology.c | 121 pal_cache_config_info_t cci; member
184 return sprintf(buf, "%u\n", 1 << this_leaf->cci.pcci_line_size); in show_coherency_line_size()
190 return sprintf(buf, "%u\n", this_leaf->cci.pcci_assoc); in show_ways_of_associativity()
197 cache_mattrib[this_leaf->cci.pcci_cache_attr]); in show_attributes()
202 return sprintf(buf, "%uK\n", this_leaf->cci.pcci_cache_size / 1024); in show_size()
207 unsigned number_of_sets = this_leaf->cci.pcci_cache_size; in show_number_of_sets()
208 number_of_sets /= this_leaf->cci.pcci_assoc; in show_number_of_sets()
209 number_of_sets /= 1 << this_leaf->cci.pcci_line_size; in show_number_of_sets()
226 int type = this_leaf->type + this_leaf->cci.pcci_unified; in show_type()
307 pal_cache_config_info_t cci; in cpu_cache_sysfs_init() local
[all …]
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| /kernel/linux/linux-6.6/arch/ia64/kernel/ |
| D | topology.c | 110 pal_cache_config_info_t cci; member
173 return sprintf(buf, "%u\n", 1 << this_leaf->cci.pcci_line_size); in show_coherency_line_size()
179 return sprintf(buf, "%u\n", this_leaf->cci.pcci_assoc); in show_ways_of_associativity()
186 cache_mattrib[this_leaf->cci.pcci_cache_attr]); in show_attributes()
191 return sprintf(buf, "%uK\n", this_leaf->cci.pcci_cache_size / 1024); in show_size()
196 unsigned number_of_sets = this_leaf->cci.pcci_cache_size; in show_number_of_sets()
197 number_of_sets /= this_leaf->cci.pcci_assoc; in show_number_of_sets()
198 number_of_sets /= 1 << this_leaf->cci.pcci_line_size; in show_number_of_sets()
215 int type = this_leaf->type + this_leaf->cci.pcci_unified; in show_type()
297 pal_cache_config_info_t cci; in cpu_cache_sysfs_init() local
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/samsung/ |
| D | exynos5420-cpus.dtsi | 63 cci-control-port = <&cci_control1>;
75 cci-control-port = <&cci_control1>;
87 cci-control-port = <&cci_control1>;
99 cci-control-port = <&cci_control1>;
111 cci-control-port = <&cci_control0>;
123 cci-control-port = <&cci_control0>;
135 cci-control-port = <&cci_control0>;
147 cci-control-port = <&cci_control0>;
|
| D | exynos5422-cpus.dtsi | 62 cci-control-port = <&cci_control0>;
75 cci-control-port = <&cci_control0>;
88 cci-control-port = <&cci_control0>;
101 cci-control-port = <&cci_control0>;
114 cci-control-port = <&cci_control1>;
127 cci-control-port = <&cci_control1>;
140 cci-control-port = <&cci_control1>;
153 cci-control-port = <&cci_control1>;
|
| /kernel/linux/linux-6.6/drivers/devfreq/ |
| D | mtk-cci-devfreq.c | 172 /* switch the cci clock to intermediate clock source. */ in mtk_ccifreq_target()
175 dev_err(dev, "failed to re-parent cci clock\n"); in mtk_ccifreq_target()
182 dev_err(dev, "failed to set cci pll rate: %d\n", ret); in mtk_ccifreq_target()
187 /* switch the cci clock back to the original clock source. */ in mtk_ccifreq_target()
190 dev_err(dev, "failed to re-parent cci clock\n"); in mtk_ccifreq_target()
267 drv->cci_clk = devm_clk_get(dev, "cci"); in mtk_ccifreq_probe()
270 return dev_err_probe(dev, ret, "failed to get cci clk\n"); in mtk_ccifreq_probe()
426 { .compatible = "mediatek,mt8183-cci", .data = &mt8183_platform_data },
427 { .compatible = "mediatek,mt8186-cci", .data = &mt8186_platform_data },
442 MODULE_DESCRIPTION("MediaTek CCI devfreq driver");
|