| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/ |
| D | intel_cdclk.c | 44 * DOC: CDCLK / RAWCLK
49 * are the core display clock (CDCLK) and RAWCLK.
51 * CDCLK clocks most of the display pipe logic, and thus its frequency
56 * On several platforms the CDCLK frequency can be changed dynamically
58 * Typically changes to the CDCLK frequency require all the display pipes
61 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
62 * DMC will not change the active CDCLK frequency however, so that part
78 u8 (*calc_voltage_level)(int cdclk);
84 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); in intel_cdclk_get_cdclk()
91 dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe); in intel_cdclk_set_cdclk()
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| D | intel_cdclk.h | 19 unsigned int cdclk, vco, ref, bypass; member
27 * Logical configuration of cdclk (used for all scaling,
34 * Actual configuration of cdclk, can be different from the
39 /* minimum acceptable cdclk to satisfy bandwidth requirements */
41 /* minimum acceptable cdclk for each pipe */
49 /* forced minimum cdclk for glk+ audio w/a */
55 /* update cdclk with pipes disabled */
83 …k_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
85 …k_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
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| D | intel_audio.c | 427 unsigned int fec_coeff, cdclk, vdsc_bpp; in calc_hblank_early_prog() local
435 cdclk = i915->display.cdclk.hw.cdclk; in calc_hblank_early_prog()
442 "lanes = %u vdsc_bpp = %u cdclk = %u\n", in calc_hblank_early_prog()
443 h_active, link_clk, lanes, vdsc_bpp, cdclk); in calc_hblank_early_prog()
445 if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bpp || !cdclk)) in calc_hblank_early_prog()
454 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk), in calc_hblank_early_prog()
455 mul_u32_u32(link_clk, cdclk)); in calc_hblank_early_prog()
887 static void get_aud_ts_cdclk_m_n(int refclk, int cdclk, struct aud_ts_cdclk_m_n *aud_ts) in get_aud_ts_cdclk_m_n() argument
890 aud_ts->n = cdclk * aud_ts->m / 24000; in get_aud_ts_cdclk_m_n()
898 get_aud_ts_cdclk_m_n(i915->display.cdclk.hw.ref, i915->display.cdclk.hw.cdclk, &aud_ts); in intel_audio_cdclk_change_post()
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| D | hsw_ips.c | 203 * the increased cdclk requirement into account when in hsw_crtc_state_ips_capable()
204 * calculating the new cdclk. in hsw_crtc_state_ips_capable()
206 * Should measure whether using a lower cdclk w/o IPS in hsw_crtc_state_ips_capable()
209 crtc_state->pixel_rate > i915->display.cdclk.max_cdclk_freq * 95 / 100) in hsw_crtc_state_ips_capable()
247 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ in hsw_ips_compute_config()
248 if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100) in hsw_ips_compute_config()
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| D | intel_display_core.h | 116 * dpll and cdclk state is protected by connection_mutex dpll.lock serializes
275 /* Display CDCLK functions */
276 const struct intel_cdclk_funcs *cdclk; member
325 /* The current hardware cdclk configuration */
328 /* cdclk, divider, and ratio table from bspec */
334 } cdclk; member
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| D | intel_display_driver.c | 86 cdclk_state = to_intel_cdclk_state(i915->display.cdclk.obj.state); in intel_display_driver_init_hw()
89 intel_cdclk_dump_config(i915, &i915->display.cdclk.hw, "Current CDCLK"); in intel_display_driver_init_hw()
90 cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw; in intel_display_driver_init_hw()
314 if (i915->display.cdclk.max_cdclk_freq == 0) in intel_display_driver_probe_nogem()
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| D | intel_atomic_plane.c | 274 * No need to check against the cdclk state if in intel_plane_calc_min_cdclk()
275 * the min cdclk for the plane doesn't increase. in intel_plane_calc_min_cdclk()
277 * Ie. we only ever increase the cdclk due to plane in intel_plane_calc_min_cdclk()
279 * display blinking due to constant cdclk changes. in intel_plane_calc_min_cdclk()
290 * No need to recalculate the cdclk state if in intel_plane_calc_min_cdclk()
291 * the min cdclk for the pipe doesn't increase. in intel_plane_calc_min_cdclk()
293 * Ie. we only ever increase the cdclk due to plane in intel_plane_calc_min_cdclk()
295 * display blinking due to constant cdclk changes. in intel_plane_calc_min_cdclk()
302 "[PLANE:%d:%s] min cdclk (%d kHz) > [CRTC:%d:%s] min cdclk (%d kHz)\n", in intel_plane_calc_min_cdclk()
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| D | intel_bw.c | 1175 * No need to check against the cdclk state if in intel_bw_calc_min_cdclk()
1176 * the min cdclk doesn't increase. in intel_bw_calc_min_cdclk()
1178 * Ie. we only ever increase the cdclk due to bandwidth in intel_bw_calc_min_cdclk()
1180 * display blinking due to constant cdclk changes. in intel_bw_calc_min_cdclk()
1190 * No need to recalculate the cdclk state if in intel_bw_calc_min_cdclk()
1191 * the min cdclk doesn't increase. in intel_bw_calc_min_cdclk()
1193 * Ie. we only ever increase the cdclk due to bandwidth in intel_bw_calc_min_cdclk()
1195 * display blinking due to constant cdclk changes. in intel_bw_calc_min_cdclk()
1201 "new bandwidth min cdclk (%d kHz) > old min cdclk (%d kHz)\n", in intel_bw_calc_min_cdclk()
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| D | intel_pmdemand.c | 292 (new_cdclk_state->actual.cdclk != in intel_pmdemand_needs_update()
293 old_cdclk_state->actual.cdclk || in intel_pmdemand_needs_update()
348 DIV_ROUND_UP(new_cdclk_state->actual.cdclk, 1000); in intel_pmdemand_atomic_check()
355 * Active_PLLs starts with 1 because of CDCLK PLL. in intel_pmdemand_atomic_check()
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| D | intel_dp_aux.c | 84 * The clock divider is based off the cdclk or PCH rawclk, and would in ilk_get_aux_clock_divider()
85 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and in ilk_get_aux_clock_divider()
89 freq = dev_priv->display.cdclk.hw.cdclk; in ilk_get_aux_clock_divider()
116 * derive the clock from CDCLK automatically). We still implement the in skl_get_aux_clock_divider()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/ |
| D | intel_cdclk.c | 33 * DOC: CDCLK / RAWCLK
38 * are the core display clock (CDCLK) and RAWCLK.
40 * CDCLK clocks most of the display pipe logic, and thus its frequency
45 * On several platforms the CDCLK frequency can be changed dynamically
47 * Typically changes to the CDCLK frequency require all the display pipes
50 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
51 * DMC will not change the active CDCLK frequency however, so that part
63 cdclk_config->cdclk = 133333; in fixed_133mhz_get_cdclk()
69 cdclk_config->cdclk = 200000; in fixed_200mhz_get_cdclk()
75 cdclk_config->cdclk = 266667; in fixed_266mhz_get_cdclk()
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| D | intel_cdclk.h | 20 u32 cdclk; member
30 * Logical configuration of cdclk (used for all scaling,
37 * Actual configuration of cdclk, can be different from the
42 /* minimum acceptable cdclk for each pipe */
50 /* forced minimum cdclk for glk+ audio w/a */
77 …to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->cdclk…
79 …to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->cdclk…
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| D | intel_atomic_plane.c | 203 * No need to check against the cdclk state if in intel_plane_calc_min_cdclk()
204 * the min cdclk for the plane doesn't increase. in intel_plane_calc_min_cdclk()
206 * Ie. we only ever increase the cdclk due to plane in intel_plane_calc_min_cdclk()
208 * display blinking due to constant cdclk changes. in intel_plane_calc_min_cdclk()
219 * No need to recalculate the cdclk state if in intel_plane_calc_min_cdclk()
220 * the min cdclk for the pipe doesn't increase. in intel_plane_calc_min_cdclk()
222 * Ie. we only ever increase the cdclk due to plane in intel_plane_calc_min_cdclk()
224 * display blinking due to constant cdclk changes. in intel_plane_calc_min_cdclk()
231 "[PLANE:%d:%s] min cdclk (%d kHz) > [CRTC:%d:%s] min cdclk (%d kHz)\n", in intel_plane_calc_min_cdclk()
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| D | intel_audio.c | 524 unsigned int fec_coeff, cdclk, vdsc_bpp; in calc_hblank_early_prog() local
532 cdclk = i915->cdclk.hw.cdclk; in calc_hblank_early_prog()
539 "lanes = %u vdsc_bpp = %u cdclk = %u\n", in calc_hblank_early_prog()
540 h_active, link_clk, lanes, vdsc_bpp, cdclk); in calc_hblank_early_prog()
542 if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bpp || !cdclk)) in calc_hblank_early_prog()
551 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk), in calc_hblank_early_prog()
552 mul_u32_u32(link_clk, cdclk)); in calc_hblank_early_prog()
1021 /* Force CDCLK to 2*BCLK as long as we need audio powered. */ in i915_audio_component_get_power()
1038 /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */ in i915_audio_component_put_power()
1077 /* Get CDCLK in kHz */
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| /kernel/linux/linux-6.6/drivers/clk/samsung/ |
| D | clk-exynos-audss.c | 128 struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in; in exynos_audss_clk_probe() local
188 cdclk = devm_clk_get(dev, "cdclk"); in exynos_audss_clk_probe()
190 if (!IS_ERR(cdclk)) in exynos_audss_clk_probe()
191 mout_i2s_p[1] = __clk_get_name(cdclk); in exynos_audss_clk_probe()
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| D | clk-s5pv210-audss.c | 70 struct clk *hclk, *pll_ref, *pll_in, *cdclk, *sclk_audio; in s5pv210_audss_clk_probe() local
105 cdclk = devm_clk_get(&pdev->dev, "iiscdclk0"); in s5pv210_audss_clk_probe()
119 if (!IS_ERR(cdclk)) in s5pv210_audss_clk_probe()
120 mout_i2s_p[1] = __clk_get_name(cdclk); in s5pv210_audss_clk_probe()
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| /kernel/linux/linux-5.10/drivers/clk/samsung/ |
| D | clk-exynos-audss.c | 129 struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in; in exynos_audss_clk_probe() local
191 cdclk = devm_clk_get(dev, "cdclk"); in exynos_audss_clk_probe()
193 if (!IS_ERR(cdclk)) in exynos_audss_clk_probe()
194 mout_i2s_p[1] = __clk_get_name(cdclk); in exynos_audss_clk_probe()
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| D | clk-s5pv210-audss.c | 71 struct clk *hclk, *pll_ref, *pll_in, *cdclk, *sclk_audio; in s5pv210_audss_clk_probe() local
109 cdclk = devm_clk_get(&pdev->dev, "iiscdclk0"); in s5pv210_audss_clk_probe()
123 if (!IS_ERR(cdclk)) in s5pv210_audss_clk_probe()
124 mout_i2s_p[1] = __clk_get_name(cdclk); in s5pv210_audss_clk_probe()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | clk-exynos-audss.txt | 26 - cdclk: External i2s clock, parent of mout_i2s. "cdclk0" is used if not
34 "pll_in", "cdclk", "sclk_audio", and "sclk_pcm_in" respectively.
82 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
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| /kernel/linux/linux-6.6/sound/hda/ |
| D | hdac_i915.c | 20 * are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
21 * BCLK = CDCLK * M / N
48 default: /* default CDCLK 450MHz */ in snd_hdac_i915_set_bclk()
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| /kernel/linux/linux-5.10/sound/hda/ |
| D | hdac_i915.c | 25 * are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
26 * BCLK = CDCLK * M / N
53 default: /* default CDCLK 450MHz */ in snd_hdac_i915_set_bclk()
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | samsung,exynos-audss-clock.yaml | 52 - const: cdclk
79 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
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| /kernel/linux/linux-5.10/include/dt-bindings/sound/ |
| D | samsung-i2s.h | 5 #define CLK_I2S_CDCLK 0 /* the CDCLK (CODECLKO) gate clock */
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| /kernel/linux/linux-6.6/include/dt-bindings/sound/ |
| D | samsung-i2s.h | 5 #define CLK_I2S_CDCLK 0 /* the CDCLK (CODECLKO) gate clock */
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| /kernel/linux/linux-5.10/include/linux/platform_data/ |
| D | asoc-s3c24xx_simtec.h | 13 * @output_cdclk: Need to output CDCLK to the codec
|