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/kernel/linux/linux-6.6/drivers/pinctrl/
Dpinctrl-ingenic.c682 INGENIC_PIN_GROUP("ssi-ce0-b", jz4755_ssi_ce0_b, 0),
683 INGENIC_PIN_GROUP("ssi-ce0-f", jz4755_ssi_ce0_f, 0),
722 "ssi-ce0-b", "ssi-ce0-f",
933 INGENIC_PIN_GROUP("ssi0-ce0-a", jz4760_ssi0_ce0_a, 2),
934 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4760_ssi0_ce0_b, 1),
935 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4760_ssi0_ce0_d, 1),
936 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4760_ssi0_ce0_e, 0),
961 INGENIC_PIN_GROUP("ssi1-ce0-b-8", jz4760_ssi1_ce0_b_8, 2),
962 INGENIC_PIN_GROUP("ssi1-ce0-b-29", jz4760_ssi1_ce0_b_29, 2),
963 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4760_ssi1_ce0_d, 2),
[all …]
Dpinctrl-gemini.c612 /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */
634 /* Serial flash pins CE0, CE1, DI, DO, CK */
655 /* The GPIO0G (17,18) pins overlap with NAND flash CE0, CE1 */
658 /* The GPIO0H (19,20) pins overlap with parallel flash CE0, CE1 */
661 /* The GPIO0I (21,22) pins overlap with serial flash CE0, CE1 */
1561 /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */
1583 /* Serial flash pins CE0, CE1, DI, DO, CK */
1601 /* The GPIO0F (17,18) pins overlap with NAND flash CE0, CE1 */
1607 /* The GPIO0H (21,22) pins overlap with serial flash CE0, CE1 */
/kernel/linux/linux-5.10/drivers/pinctrl/
Dpinctrl-ingenic.c862 INGENIC_PIN_GROUP("ssi0-ce0-a", jz4770_ssi0_ce0_a),
863 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4770_ssi0_ce0_b),
864 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4770_ssi0_ce0_d),
865 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e),
881 INGENIC_PIN_GROUP("ssi1-ce0-b", jz4770_ssi1_ce0_b),
882 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4770_ssi1_ce0_d),
883 INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e),
944 "ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
952 "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e",
1170 INGENIC_PIN_GROUP("ssi0-ce0-a-23", jz4780_ssi0_ce0_a_23),
[all …]
Dpinctrl-gemini.c610 /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */
632 /* Serial flash pins CE0, CE1, DI, DO, CK */
653 /* The GPIO0G (17,18) pins overlap with NAND flash CE0, CE1 */
656 /* The GPIO0H (19,20) pins overlap with parallel flash CE0, CE1 */
659 /* The GPIO0I (21,22) pins overlap with serial flash CE0, CE1 */
1559 /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */
1581 /* Serial flash pins CE0, CE1, DI, DO, CK */
1599 /* The GPIO0F (17,18) pins overlap with NAND flash CE0, CE1 */
1605 /* The GPIO0H (21,22) pins overlap with serial flash CE0, CE1 */
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/wireless/
Dqcom,ath11k.yaml33 - description: interrupt event for ring CE0
89 - const: ce0
226 "ce0",
/kernel/linux/linux-6.6/arch/mips/boot/dts/ingenic/
Dcu1830-neo.dts78 reg = <0>; /* CE0 */
197 groups = "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-ce0", "ssi0-ce1";
Dcu1000-neo.dts79 reg = <0>; /* CE0 */
194 groups = "ssi-dt-d", "ssi-dr-d", "ssi-clk-d", "ssi-ce0-d";
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/spi/
Dsony-cxd2880.txt16 reg = <0>; /* CE0 */
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/media/spi/
Dsony-cxd2880.txt16 reg = <0>; /* CE0 */
/kernel/linux/linux-5.10/drivers/mtd/spi-nor/controllers/
Daspeed-smc.c38 u8 we0; /* shift for write enable bit for CE0 */
39 u8 ctl0; /* offset in regs of ctl for CE0 */
119 * CE0 and CE1 can only be of type SPI. CE2 can be of type NOR but the
546 * The AST2500 SPI controller has a HW bug when the CE0 chip in aspeed_smc_chip_set_segment()
563 * start address if we are handling CE0 or use the previous in aspeed_smc_chip_set_segment()
637 * register. It uses the CE0 control register to set 4Byte mode at the
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/wireless/
Dqcom,ath11k.yaml105 - description: interrupt event for ring CE0
159 - const: ce0
332 "ce0",
Dqcom,ath10k.yaml245 - description: CE0
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dgemini-rut1xx.dts52 /* Conflict with NAND CE0 */
Dgemini-sl93512r.dts64 /* Conflict with NAND flash CE0 (no problem) */
Dsun7i-a20-bananapi.dts247 "", "", "SPI-CE0", "SPI-CLK", "SPI-MOSI",
/kernel/linux/linux-6.6/arch/arm/boot/dts/gemini/
Dgemini-rut1xx.dts52 /* Conflict with NAND CE0 */
Dgemini-sl93512r.dts64 /* Conflict with NAND flash CE0 (no problem) */
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/top/
Dgk104.c79 case 0x00000001: A_(CE0 ); break; in gk104_top_oneinit()
/kernel/linux/linux-6.6/drivers/net/wireless/ath/ath11k/
Dce.c12 /* CE0: host->target HTC control and raw streams */
118 /* CE0: host->target HTC control and raw streams */
198 /* CE0: host->target HTC control and raw streams */
/kernel/linux/linux-6.6/arch/riscv/boot/dts/allwinner/
Dsun20i-d1-nezha.dts230 "pin24 [gpio16/spi1-ce0]",
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/core/
Dsubdev.c59 [NVKM_ENGINE_CE0 ] = "ce0",
/kernel/linux/linux-6.6/arch/arm/boot/dts/allwinner/
Dsun7i-a20-bananapi.dts246 "", "", "SPI-CE0", "SPI-CLK", "SPI-MOSI",
/kernel/linux/linux-6.6/drivers/net/wireless/ath/ath12k/
Dce.c12 /* CE0: host->target HTC control and raw streams */
146 /* CE0: host->target HTC control and raw streams */
/kernel/linux/linux-6.6/drivers/spi/
Dspi-aspeed-smc.c496 * Due to an HW issue on the AST2500 SPI controller, the CE0 in aspeed_spi_chip_adjust_window()
604 * CE0 Control Register in aspeed_spi_dirmap_create()
890 * The timing register is shared by all devices. Only update for CE0.
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
Dgv100.c168 { 0x01, "CE0" },

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