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Searched +full:cfgr +full:- +full:clk (Results 1 – 22 of 22) sorted by relevance

/kernel/linux/linux-5.10/drivers/mmc/host/
Dmmci_stm32_sdmmc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
8 #include <linux/dma-mapping.h>
64 for_each_sg(data->sg, sg, data->sg_len - 1, i) { in sdmmc_idma_validate_data()
65 if (!IS_ALIGNED(sg->offset, sizeof(u32)) || in sdmmc_idma_validate_data()
66 !IS_ALIGNED(sg->length, SDMMC_IDMA_BURST)) { in sdmmc_idma_validate_data()
67 dev_err(mmc_dev(host->mmc), in sdmmc_idma_validate_data()
69 data->sg->offset, data->sg->length); in sdmmc_idma_validate_data()
70 return -EINVAL; in sdmmc_idma_validate_data()
74 if (!IS_ALIGNED(sg->offset, sizeof(u32))) { in sdmmc_idma_validate_data()
[all …]
/kernel/linux/linux-5.10/drivers/pwm/
Dpwm-stm32-lp.c1 // SPDX-License-Identifier: GPL-2.0
3 * STM32 Low-Power Timer PWM driver
9 * Inspired by Gerald Baeza's pwm-stm32 driver
13 #include <linux/mfd/stm32-lptimer.h>
22 struct clk *clk; member
31 /* STM32 Low-Power Timer is preceded by a configurable power-of-2 prescaler */
40 u32 val, mask, cfgr, presc = 0; in stm32_pwm_lp_apply() local
47 if (!state->enabled) { in stm32_pwm_lp_apply()
50 ret = regmap_write(priv->regmap, STM32_LPTIM_CR, 0); in stm32_pwm_lp_apply()
54 clk_disable(priv->clk); in stm32_pwm_lp_apply()
[all …]
/kernel/linux/linux-6.6/drivers/pwm/
Dpwm-stm32-lp.c1 // SPDX-License-Identifier: GPL-2.0
3 * STM32 Low-Power Timer PWM driver
9 * Inspired by Gerald Baeza's pwm-stm32 driver
13 #include <linux/mfd/stm32-lptimer.h>
22 struct clk *clk; member
31 /* STM32 Low-Power Timer is preceded by a configurable power-of-2 prescaler */
40 u32 val, mask, cfgr, presc = 0; in stm32_pwm_lp_apply() local
47 if (!state->enabled) { in stm32_pwm_lp_apply()
50 ret = regmap_write(priv->regmap, STM32_LPTIM_CR, 0); in stm32_pwm_lp_apply()
54 clk_disable(priv->clk); in stm32_pwm_lp_apply()
[all …]
/kernel/linux/linux-6.6/drivers/mmc/host/
Dmmci_stm32_sdmmc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
8 #include <linux/dma-mapping.h>
84 struct sdmmc_idma *idma = host->dma_priv; in sdmmc_idma_validate_data()
85 struct device *dev = mmc_dev(host->mmc); in sdmmc_idma_validate_data()
93 idma->use_bounce_buffer = false; in sdmmc_idma_validate_data()
94 for_each_sg(data->sg, sg, data->sg_len - 1, i) { in sdmmc_idma_validate_data()
95 if (!IS_ALIGNED(sg->offset, sizeof(u32)) || in sdmmc_idma_validate_data()
96 !IS_ALIGNED(sg->length, in sdmmc_idma_validate_data()
97 host->variant->stm32_idmabsize_align)) { in sdmmc_idma_validate_data()
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/dma/
Dsnps,dw-axi-dmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
16 - $ref: dma-controller.yaml#
21 - snps,axi-dma-1.01a
22 - intel,kmb-axi-dma
23 - starfive,jh7110-axi-dma
28 - description: Address range of the DMAC registers
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/kernel/linux/linux-5.10/sound/soc/stm/
Dstm32_i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
10 #include <linux/clk.h>
134 #define I2S_CGFR_I2SDIV_MAX ((1 << (I2S_CGFR_I2SDIV_BIT_H -\
135 I2S_CGFR_I2SDIV_SHIFT)) - 1)
196 #define STM32_I2S_IS_MASTER(x) ((x)->ms_flg == I2S_MS_MASTER)
197 #define STM32_I2S_IS_SLAVE(x) ((x)->ms_flg == I2S_MS_SLAVE)
200 * struct stm32_i2s_data - private data of I2S
229 struct clk *i2sclk;
230 struct clk *pclk;
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/kernel/linux/linux-6.6/sound/soc/stm/
Dstm32_i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
136 #define I2S_CGFR_I2SDIV_MAX ((1 << (I2S_CGFR_I2SDIV_BIT_H -\
137 I2S_CGFR_I2SDIV_SHIFT)) - 1)
198 #define STM32_I2S_IS_MASTER(x) ((x)->ms_flg == I2S_MS_MASTER)
199 #define STM32_I2S_IS_SLAVE(x) ((x)->ms_flg == I2S_MS_SLAVE)
205 * struct stm32_i2s_data - private data of I2S
238 struct clk *i2sclk;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/dma/
Dsnps,dw-axi-dmac.txt4 - compatible: "snps,axi-dma-1.01a"
5 - reg: Address range of the DMAC registers. This should include
6 all of the per-channel registers.
7 - interrupt: Should contain the DMAC interrupt number.
8 - dma-channels: Number of channels supported by hardware.
9 - snps,dma-masters: Number of AXI masters supported by the hardware.
10 - snps,data-width: Maximum AXI data width supported by hardware.
11 (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
12 - snps,priority: Priority of channel. Array size is equal to the number of
13 dma-channels. Priority value must be programmed within [0:dma-channels-1]
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/kernel/linux/linux-5.10/drivers/pinctrl/
Dpinctrl-at91-pio4.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/pinctrl/at91.h>
10 #include <linux/clk.h>
18 #include <linux/pinctrl/pinconf-generic.h>
24 #include "pinctrl-utils.h"
93 * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio)
95 * @clk: clock of the controller.
116 struct clk *clk; member
130 u32 cfgr[ATMEL_PIO_NPINS_PER_BANK]; member
141 {"atmel,drive-strength", ATMEL_PIN_CONFIG_DRIVE_STRENGTH, 0},
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/kernel/linux/linux-6.6/arch/arm64/boot/dts/intel/
Dsocfpga_agilex5.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/clock/intel,agilex5-clkmgr.h>
14 compatible = "intel,socfpga-agilex5";
15 #address-cells = <2>;
16 #size-cells = <2>;
[all …]
/kernel/linux/linux-6.6/drivers/pinctrl/
Dpinctrl-at91-pio4.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/pinctrl/at91.h>
11 #include <linux/clk.h>
21 #include <linux/pinctrl/pinconf-generic.h>
28 #include "pinctrl-utils.h"
80 * struct atmel_pioctrl_data - Atmel PIO controller (pinmux + gpio) data struct
107 * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio)
109 * @clk: clock of the controller.
131 struct clk *clk; member
145 u32 cfgr[ATMEL_PIO_NPINS_PER_BANK]; member
[all …]
/kernel/linux/linux-5.10/arch/arc/boot/dts/
Dhsdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/reset/snps,hsdk-reset.h>
18 #address-cells = <2>;
19 #size-cells = <2>;
22 … "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
30 #address-cells = <1>;
31 #size-cells = <0>;
62 input_clk: input-clk {
[all …]
/kernel/linux/linux-6.6/arch/arc/boot/dts/
Dhsdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/reset/snps,hsdk-reset.h>
18 #address-cells = <2>;
19 #size-cells = <2>;
22 … "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
30 #address-cells = <1>;
31 #size-cells = <0>;
62 input_clk: input-clk {
[all …]
/kernel/linux/linux-6.6/arch/riscv/boot/dts/thead/
Dth1520.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <1>;
16 #size-cells = <0>;
17 timebase-frequency = <3000000>;
24 i-cache-block-size = <64>;
25 i-cache-size = <65536>;
26 i-cache-sets = <512>;
[all …]
/kernel/linux/linux-6.6/arch/riscv/boot/dts/canaan/
Dk210.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
6 #include <dt-bindings/clock/k210-clk.h>
7 #include <dt-bindings/pinctrl/k210-fpioa.h>
8 #include <dt-bindings/reset/k210-rst.h>
12 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
15 #address-cells = <1>;
16 #size-cells = <1>;
17 compatible = "canaan,kendryte-k210";
28 * Since this is a non-ratified draft specification, the kernel does not
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/kernel/linux/linux-5.10/drivers/dma/dw-axi-dmac/
Ddw-axi-dmac-platform.c1 // SPDX-License-Identifier: GPL-2.0
2 // (C) 2017-2018 Synopsys, Inc. (www.synopsys.com)
26 #include "dw-axi-dmac.h"
28 #include "../virt-dma.h"
47 iowrite32(val, chip->regs + reg); in axi_dma_iowrite32()
52 return ioread32(chip->regs + reg); in axi_dma_ioread32()
58 iowrite32(val, chan->chan_regs + reg); in axi_chan_iowrite32()
63 return ioread32(chan->chan_regs + reg); in axi_chan_ioread32()
73 iowrite32(lower_32_bits(val), chan->chan_regs + reg); in axi_chan_iowrite64()
74 iowrite32(upper_32_bits(val), chan->chan_regs + reg + 4); in axi_chan_iowrite64()
[all …]
/kernel/linux/linux-6.6/sound/soc/atmel/
Dmchp-pdmc.c1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright (C) 2019-2022 Microchip Technology Inc. and its subsidiaries
9 #include <dt-bindings/sound/microchip,pdmc.h>
12 #include <linux/clk.h>
24 * ---- PDMC Register map ----
37 * ---- Control Register (Write-only) ----
42 * ---- Mode Register (Read/Write) ----
66 * ---- Configuration Register (Read/Write) ----
75 * ---- Interrupt Enable/Disable/Mask/Status Registers ----
85 * ---- Version Register (Read-only) ----
[all …]
/kernel/linux/linux-6.6/arch/riscv/boot/dts/starfive/
Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/freescale/
Dfec_main.c1 // SPDX-License-Identifier: GPL-2.0+
17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
20 * Copyright (c) 2004-2006 Macq Electronique SA.
22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
50 #include <linux/clk.h>
142 .name = "imx25-fec",
145 .name = "imx27-fec",
148 .name = "imx28-fec",
151 .name = "imx6q-fec",
154 .name = "mvf600-fec",
[all …]
/kernel/linux/linux-6.6/drivers/dma/dw-axi-dmac/
Ddw-axi-dmac-platform.c1 // SPDX-License-Identifier: GPL-2.0
2 // (C) 2017-2018 Synopsys, Inc. (www.synopsys.com)
15 #include <linux/dma-mapping.h>
20 #include <linux/io-64-nonatomic-lo-hi.h>
32 #include "dw-axi-dmac.h"
34 #include "../virt-dma.h"
57 iowrite32(val, chip->regs + reg); in axi_dma_iowrite32()
62 return ioread32(chip->regs + reg); in axi_dma_ioread32()
68 iowrite32(val, chan->chan_regs + reg); in axi_chan_iowrite32()
73 return ioread32(chan->chan_regs + reg); in axi_chan_ioread32()
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/freescale/
Dfec_main.c1 // SPDX-License-Identifier: GPL-2.0+
17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
20 * Copyright (c) 2004-2006 Macq Electronique SA.
22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
52 #include <linux/clk.h>
190 .name = "imx25-fec",
193 .name = "imx27-fec",
196 .name = "imx28-fec",
199 .name = "imx6q-fec",
202 .name = "mvf600-fec",
[all …]
/kernel/linux/patches/linux-5.10/imx8mm_patch/patches/drivers/
D0030_linux_drivers_pci_misc_nvmem_of_mtd_mmc.patch7 Change-Id: Iec160bd007994d82f416debdccfbc0d9bdb40470
9 diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
11 --- a/drivers/misc/Kconfig
13 @@ -314,6 +314,26 @@ config ISL29020
40 diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
42 --- a/drivers/misc/Makefile
44 @@ -19,6 +19,8 @@ obj-$(CONFIG_TIFM_7XX1) += tifm_7xx1.o
45 obj-$(CONFIG_PHANTOM) += phantom.o
46 obj-$(CONFIG_QCOM_COINCELL) += qcom-coincell.o
47 obj-$(CONFIG_QCOM_FASTRPC) += fastrpc.o
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