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/kernel/linux/linux-6.6/drivers/mtd/chips/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "RAM/ROM/Flash chip drivers"
6 tristate "Detect flash chips by Common Flash Interface (CFI) probe"
10 The Common Flash Interface specification was developed by Intel,
11 AMD and other flash manufactures that provides a universal method
12 for probing the capabilities of flash devices. If you wish to
13 support any device that is CFI-compliant, you need to enable this
14 option. Visit <https://www.amd.com/products/nvd/overview/cfi.html>
15 for more information on CFI.
18 tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
[all …]
Dcfi_cmdset_0002.c1 // SPDX-License-Identifier: GPL-2.0
3 * Common Flash Interface support:
14 * XIP support hooks by Vitaly Wool (based on code for Intel flash
17 * 25/09/2008 Christopher Moore: TopBottom fixup for many Macronix with CFI V1.0
37 #include <linux/mtd/cfi.h>
52 * Status Register bit description. Used by flash devices that don't
118 * CFI Primary Vendor-Specific Extended Query table 1.5
120 static int cfi_use_status_reg(struct cfi_private *cfi) in cfi_use_status_reg() argument
122 struct cfi_pri_amdstd *extp = cfi->cmdset_priv; in cfi_use_status_reg()
125 return extp && extp->MinorVersion >= '5' && in cfi_use_status_reg()
[all …]
Dcfi_cmdset_0001.c1 // SPDX-License-Identifier: GPL-2.0
3 * Common Flash Interface support:
10 * - completely revamped method functions so they are aware and
11 * independent of the flash geometry (buswidth, interleave, etc.)
12 * - scalability vs code size is completely set at compile-time
13 * (see include/linux/mtd/cfi.h for selection)
14 * - optimized write buffer method
16 * - reworked lock/unlock/erase support for var size flash
18 * - auto unlock sectors on resume for auto locking flash on power up
37 #include <linux/mtd/cfi.h>
[all …]
Dcfi_probe.c1 // SPDX-License-Identifier: GPL-2.0
3 Common Flash Interface probe code.
19 #include <linux/mtd/cfi.h>
29 unsigned long *chip_map, struct cfi_private *cfi);
30 static int cfi_chip_setup(struct map_info *map, struct cfi_private *cfi);
46 #define xip_enable(base, map, cfi) \ argument
48 cfi_qry_mode_off(base, map, cfi); \
52 #define xip_disable_qry(base, map, cfi) \ argument
55 cfi_qry_mode_on(base, map, cfi); \
62 #define xip_enable(base, map, cfi) do { } while (0) argument
[all …]
Dcfi_util.c1 // SPDX-License-Identifier: GPL-2.0
3 * Common Flash Interface support:
23 #include <linux/mtd/cfi.h>
40 struct map_info *map, struct cfi_private *cfi) in cfi_build_cmd_addr() argument
43 unsigned interleave = cfi_interleave(cfi); in cfi_build_cmd_addr()
44 unsigned type = cfi->device_type; in cfi_build_cmd_addr()
62 * Transforms the CFI command for the given geometry (bus width & interleave).
66 map_word cfi_build_cmd(u_long cmd, struct map_info *map, struct cfi_private *cfi) in cfi_build_cmd() argument
85 chip_mode = map_bankwidth(map) / cfi_interleave(cfi); in cfi_build_cmd()
86 chips_per_word = wordwidth * cfi_interleave(cfi) / map_bankwidth(map); in cfi_build_cmd()
[all …]
/kernel/linux/linux-5.10/drivers/mtd/chips/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "RAM/ROM/Flash chip drivers"
6 tristate "Detect flash chips by Common Flash Interface (CFI) probe"
10 The Common Flash Interface specification was developed by Intel,
11 AMD and other flash manufactures that provides a universal method
12 for probing the capabilities of flash devices. If you wish to
13 support any device that is CFI-compliant, you need to enable this
14 option. Visit <https://www.amd.com/products/nvd/overview/cfi.html>
15 for more information on CFI.
18 tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
[all …]
Dcfi_cmdset_0002.c2 * Common Flash Interface support:
13 * XIP support hooks by Vitaly Wool (based on code for Intel flash
16 * 25/09/2008 Christopher Moore: TopBottom fixup for many Macronix with CFI V1.0
39 #include <linux/mtd/cfi.h>
53 * Status Register bit description. Used by flash devices that don't
119 * CFI Primary Vendor-Specific Extended Query table 1.5
121 static int cfi_use_status_reg(struct cfi_private *cfi) in cfi_use_status_reg() argument
123 struct cfi_pri_amdstd *extp = cfi->cmdset_priv; in cfi_use_status_reg()
126 return extp && extp->MinorVersion >= '5' && in cfi_use_status_reg()
127 (extp->SoftwareFeatures & poll_mask) == CFI_POLL_STATUS_REG; in cfi_use_status_reg()
[all …]
Dcfi_cmdset_0001.c2 * Common Flash Interface support:
9 * - completely revamped method functions so they are aware and
10 * independent of the flash geometry (buswidth, interleave, etc.)
11 * - scalability vs code size is completely set at compile-time
12 * (see include/linux/mtd/cfi.h for selection)
13 * - optimized write buffer method
15 * - reworked lock/unlock/erase support for var size flash
17 * - auto unlock sectors on resume for auto locking flash on power up
36 #include <linux/mtd/cfi.h>
122 printk(" Extended Query version %c.%c\n", extp->MajorVersion, extp->MinorVersion); in cfi_tell_features()
[all …]
Dcfi_probe.c2 Common Flash Interface probe code.
18 #include <linux/mtd/cfi.h>
28 unsigned long *chip_map, struct cfi_private *cfi);
29 static int cfi_chip_setup(struct map_info *map, struct cfi_private *cfi);
45 #define xip_enable(base, map, cfi) \ argument
47 cfi_qry_mode_off(base, map, cfi); \
51 #define xip_disable_qry(base, map, cfi) \ argument
54 cfi_qry_mode_on(base, map, cfi); \
61 #define xip_enable(base, map, cfi) do { } while (0) argument
62 #define xip_disable_qry(base, map, cfi) do { } while (0) argument
[all …]
Dcfi_util.c2 * Common Flash Interface support:
24 #include <linux/mtd/cfi.h>
41 struct map_info *map, struct cfi_private *cfi) in cfi_build_cmd_addr() argument
44 unsigned interleave = cfi_interleave(cfi); in cfi_build_cmd_addr()
45 unsigned type = cfi->device_type; in cfi_build_cmd_addr()
63 * Transforms the CFI command for the given geometry (bus width & interleave).
67 map_word cfi_build_cmd(u_long cmd, struct map_info *map, struct cfi_private *cfi) in cfi_build_cmd() argument
86 chip_mode = map_bankwidth(map) / cfi_interleave(cfi); in cfi_build_cmd()
87 chips_per_word = wordwidth * cfi_interleave(cfi) / map_bankwidth(map); in cfi_build_cmd()
89 /* First, determine what the bit-pattern should be for a single in cfi_build_cmd()
[all …]
/kernel/linux/linux-5.10/drivers/mtd/maps/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
7 bool "Support non-linear mappings of flash chips"
10 paged mappings of flash chips.
13 tristate "Flash device in physical memory map"
16 This provides a 'mapping' driver which allows the NOR Flash and
19 the physical address and size of the flash chips on your
21 with config options or at run-time.
38 hex "Physical start address of flash mapping"
42 This is the physical memory location at which the flash chips
48 hex "Physical length of flash mapping"
[all …]
Dscb2_flash.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * MTD map driver for BIOS Flash on Intel SCB2 boards
20 * * D8-D15 ignored
25 * logical address 0 hit higher-address sections of the chip, not physical 0.
29 * This driver assumes the chip is not write-protected by an external signal.
33 * updates for this board include 10 related (*.bio - &.bi9) binary files and
40 * offset 0x00000 to 0x4ffff (320k): unknown - SCSI BIOS, etc?
54 #include <linux/mtd/cfi.h>
66 .name = "SCB2 BIOS Flash",
76 struct map_info *map = mtd->priv; in scb2_fixup_mtd()
[all …]
/kernel/linux/linux-6.6/drivers/mtd/maps/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
7 bool "Support non-linear mappings of flash chips"
10 paged mappings of flash chips.
13 tristate "Flash device in physical memory map"
16 This provides a 'mapping' driver which allows the NOR Flash and
19 the physical address and size of the flash chips on your
21 with config options or at run-time.
38 hex "Physical start address of flash mapping"
42 This is the physical memory location at which the flash chips
48 hex "Physical length of flash mapping"
[all …]
Dscb2_flash.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * MTD map driver for BIOS Flash on Intel SCB2 boards
20 * * D8-D15 ignored
25 * logical address 0 hit higher-address sections of the chip, not physical 0.
29 * This driver assumes the chip is not write-protected by an external signal.
33 * updates for this board include 10 related (*.bio - &.bi9) binary files and
40 * offset 0x00000 to 0x4ffff (320k): unknown - SCSI BIOS, etc?
54 #include <linux/mtd/cfi.h>
66 .name = "SCB2 BIOS Flash",
76 struct map_info *map = mtd->priv; in scb2_fixup_mtd()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/
Dmtd-physmap.txt1 CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...)
3 Flash chips (Memory Technology Devices) are often used for solid state
6 - compatible : should contain the specific model of mtd chip(s)
7 used, if known, followed by either "cfi-flash", "jedec-flash",
8 "mtd-ram" or "mtd-rom".
9 - reg : Address range(s) of the mtd chip(s)
11 non-identical chips can be described in one node.
12 - bank-width : Width (in bytes) of the bank. Equal to the
14 - device-width : (optional) Width of a single mtd chip. If
15 omitted, assumed to be equal to 'bank-width'.
[all …]
Dintel,ixp4xx-flash.txt1 Flash device on Intel IXP4xx SoC
3 This flash is regular CFI compatible (Intel or AMD extended) flash chips with
4 specific big-endian or mixed-endian memory access pattern.
7 - compatible : must be "intel,ixp4xx-flash", "cfi-flash";
8 - reg : memory address for the flash chip
9 - bank-width : width in bytes of flash interface, should be <2>
11 For the rest of the properties, see mtd-physmap.txt.
13 The device tree may optionally contain sub-nodes describing partitions of the
18 flash@50000000 {
19 compatible = "intel,ixp4xx-flash", "cfi-flash";
[all …]
Dcortina,gemini-flash.txt1 Flash device on Cortina Systems Gemini SoC
3 This flash is regular CFI compatible (Intel or AMD extended) flash chips with
7 - compatible : must be "cortina,gemini-flash", "cfi-flash";
8 - reg : memory address for the flash chip
9 - syscon : must be a phandle to the system controller
10 - bank-width : width in bytes of flash interface, should be <2>
12 For the rest of the properties, see mtd-physmap.txt.
14 The device tree may optionally contain sub-nodes describing partitions of the
19 flash@30000000 {
20 compatible = "cortina,gemini-flash", "cfi-flash";
[all …]
Darm-versatile.txt1 Flash device on ARM Versatile board
3 These flash chips are found in the ARM reference designs like Integrator,
6 They are regular CFI compatible (Intel or AMD extended) flash chips with
11 - compatible : must be "arm,versatile-flash", "cfi-flash";
12 - reg : memory address for the flash chip
13 - bank-width : width in bytes of flash interface.
15 For the rest of the properties, see mtd-physmap.txt.
17 The device tree may optionally contain sub-nodes describing partitions of the
22 flash@34000000 {
23 compatible = "arm,versatile-flash", "cfi-flash";
[all …]
Dcypress,hyperflash.txt1 Bindings for HyperFlash NOR flash chips compliant with Cypress HyperBus
2 specification and supports Cypress CFI specification 1.5 command set.
5 - compatible : "cypress,hyperflash", "cfi-flash" for HyperFlash NOR chips
6 - reg : Address of flash's memory map
10 flash@0 {
11 compatible = "cypress,hyperflash", "cfi-flash";
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mtd/
Dmtd-physmap.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/mtd-physmap.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...)
10 - Rob Herring <robh@kernel.org>
13 Flash chips (Memory Technology Devices) are often used for solid state
17 - $ref: mtd.yaml#
18 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
23 - items:
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dpl353-smc.txt8 - compatible : Should be "arm,pl353-smc-r2p1", "arm,primecell".
9 - reg : Controller registers map and length.
10 - clock-names : List of input clock names - "memclk", "apb_pclk"
12 - clocks : Clock phandles (see clock bindings for details).
13 - address-cells : Must be 2.
14 - size-cells : Must be 1.
17 For NAND the "arm,pl353-nand-r2p1" and for NOR the "cfi-flash" drivers are
24 smcc: memory-controller@e000e000
25 compatible = "arm,pl353-smc-r2p1", "arm,primecell";
26 clock-names = "memclk", "apb_pclk";
[all …]
Drenesas,rpc-if.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/renesas,rpc-if.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Reduced Pin Count Interface (RPC-IF)
10 - Sergei Shtylyov <sergei.shtylyov@gmail.com>
13 Renesas RPC-IF allows a SPI flash or HyperFlash connected to the SoC to
16 The flash chip itself should be represented by a subnode of the RPC-IF node.
17 The flash interface is selected based on the "compatible" property of this
19 - if it contains "jedec,spi-nor", then SPI is used;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/fsl/
Difc.txt1 Integrated Flash Controller
4 - name : Should be ifc
5 - compatible : should contain "fsl,ifc". The version of the integrated
6 flash controller can be found in the IFC_REV register at
9 - #address-cells : Should be either two or three. The first cell is the
12 - #size-cells : Either one or two, depending on how large each chipselect
14 - reg : Offset and length of the register set for the device
15 - interrupts: IFC may have one or two interrupts. If two interrupt
21 - little-endian : If this property is absent, the big-endian mode will
24 - ranges : Each range corresponds to a single chipselect, and covers
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/
Dsbc8548.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
11 /dts-v1/;
13 /include/ "sbc8548-pre.dtsi"
17 #address-cells = <2>;
18 #size-cells = <1>;
19 compatible = "simple-bus";
21 interrupt-parent = <&mpic>;
23 ranges = <0x0 0x0 0xff800000 0x00800000 /*8MB Flash*/
27 0x6 0x0 0xec000000 0x04000000>; /*64MB Flash*/
30 flash@0,0 {
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/memory-controllers/fsl/
Dfsl,ifc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,ifc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: FSL/NXP Integrated Flash Controller
10 - Li Yang <leoyang.li@nxp.com>
13 NXP's integrated flash controller (IFC) is an advanced version of the
16 external memory types, such as NAND flash (SLC and MLC), NOR flash, EPROM,
21 pattern: "^memory-controller@[0-9a-f]+$"
26 "#address-cells":
[all …]

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